[PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache
arnd at arndb.de
Sat Feb 15 08:23:23 EST 2014
On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote:
> Instantiate the L2 cache from DT. Indicate in DT where the cache
> control register is and if write through should be made.
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> cc: devicetree at vger.kernel.org
I guess this answers part of my question for patch 5, but I also
wonder if the run-time setting is correct now with the hardcoded
#ifdef in arch/arm/mm/proc-feroceon.S checkign for the
Kconfig option. Presumably the code should match whatever is
set in the cache control register.
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