[PATCH RFC v3 3/3] Documentation: arm: define DT idle states bindings
Lorenzo Pieralisi
lorenzo.pieralisi at arm.com
Tue Feb 11 09:17:53 EST 2014
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.
Therefore, this patch aims at standardizing idle state device tree bindings for
ARM platforms. Bindings define idle state parameters inclusive of entry methods
and state latencies, to allow operating systems to retrieve the configuration
entries from the device tree and initialize the related power management
drivers, paving the way for common code in the kernel to deal with idle
states and removing the need for static data in current and previous kernel
versions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 10 +
Documentation/devicetree/bindings/arm/idle-states.txt | 690 ++++++++++
2 files changed, 700 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..fb7f008 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,13 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
+ - cpu-idle-states
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition:
+ # List of phandles to cpu idle state nodes supported
+ by this cpu [1].
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@@ -382,3 +389,6 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+[1] ARM Linux kernel documentation - idle state bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 0000000..f155e70
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,690 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OSPM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+1 - Running
+2 - Idle_standby
+3 - Idle_retention
+4 - Sleep
+5 - Off
+
+ARM platforms implement the power states specified in the SBSA through power
+management schemes that allow an OS PM implementation to put the processor in
+different idle states (which include states 1 to 4 above; "off" state is not
+an idle state since it does not have wake-up capabilities, hence it is not
+considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OSPM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - cpu-idle-states node
+===========================================
+
+ARM processor idle states are defined within the cpu-idle-states node, which is
+a direct child of the cpus node and provides a container where the processor
+states, defined as device tree nodes, are listed.
+
+- cpu-idle-states node
+
+ Usage: Optional - On ARM systems, is a container of processor idle
+ states nodes. If the system does not provide CPU
+ power management capabilities or the processor just
+ supports idle_standby a cpu-idle-states node is not
+ required.
+
+ Description: cpu-idle-states node is a container node, where its
+ subnodes describe the CPU idle states.
+
+ Node name must be "cpu-idle-states".
+
+ The cpu-idle-states node's parent node must be the cpus node.
+
+ The cpu-idle-states node's child nodes can be:
+
+ - one or more state nodes
+
+ Any other configuration is considered invalid.
+
+The nodes describing the idle states (state) can only be defined within the
+cpu-idle-states node.
+
+Any other configuration is consider invalid and therefore must be ignored.
+
+===========================================
+2 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+ Description: must be child of either the cpu-idle-states node or
+ a state node.
+
+ The state node name shall be "stateN", where N = {0, 1, ...} is
+ the node number; state nodes which are siblings within a single common
+ parent node must be given a unique and sequential N value, starting
+ from 0.
+
+ A state node can contain state child nodes. A state node with
+ children represents a hierarchical state, which is a superset of
+ the child states. Hierarchical states require all CPUs on which
+ they are valid to request the state in order for it to be entered.
+
+ A state node defines the following properties:
+
+ - compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must be "arm,cpu-idle-state".
+
+ - index
+ Usage: Required
+ Value type: <u32>
+ Definition: It represents an idle state index, starting from 2.
+ Index 0 represents the processor state "running"
+ and index 1 represents processor mode
+ "idle_standby", entered by executing a wfi
+ instruction (SBSA,[3]); indexes 0 and 1 are
+ standard ARM states that need not be described.
+
+ - entry-method
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Describes the method by which a CPU enters the
+ idle state. This property is required and must be
+ one of:
+
+ - "arm,psci-cpu-suspend"
+ ARM PSCI firmware interface, CPU suspend
+ method[2].
+
+ - "[vendor],[method]"
+ An implementation dependent string with
+ format "vendor,method", where vendor is a string
+ denoting the name of the manufacturer and
+ method is a string specifying the mechanism
+ used to enter the idle state.
+
+ - power-state
+ Usage: See definition.
+ Value type: <u32>
+ Definition: Depends on the entry-method property value.
+ If entry-method is "arm,psci-cpu-suspend":
+ # Property is required and represents
+ psci-power-state parameter. Please refer to
+ [2] for PSCI bindings definition.
+
+ - entry-latency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to enter the idle state.
+
+ - exit-latency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to exit the idle state.
+
+ - min-residency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing time in microseconds
+ required for the CPU to be in the idle state to
+ make up for the dynamic power consumed to
+ enter/exit the idle state in order to break even
+ in terms of power consumption compared to idle
+ state index 1 (idle_standby).
+
+ - power-domains
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition: List of power domain specifiers ([1]) describing
+ the power domains that are affected by the idle
+ state entry.
+
+ - cache-state-retained
+ Usage: See definition
+ Value type: <none>
+ Definition: if present cache memory is retained on power down,
+ otherwise it is lost.
+
+ - processor-state-retained
+ Usage: See definition
+ Value type: <none>
+ Definition: if present CPU processor logic is retained on
+ power down, otherwise it is lost.
+
+===========================================
+3 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system):
+
+pd_clusters: power-domain-clusters at 80002000 {
+ compatible = "arm,power-controller";
+ reg = <0x0 0x80002000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pd_cores: power-domain-cores at 80000000 {
+ compatible = "arm,power-controller";
+ reg = <0x0 0x80000000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+};
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu-idle-states {
+
+ STATE0: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <3>;
+ entry-method = "arm,psci-cpu-suspend";
+ psci-power-state = <0x1010000>;
+ entry-latency = <500>;
+ exit-latency = <1000>;
+ min-residency = <2500>;
+ power-domains = <&pd_clusters 0>;
+ STATE0_1: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <2>;
+ entry-method = "arm,psci-cpu-suspend";
+ psci-power-state = <0x0010000>;
+ entry-latency = <200>;
+ exit-latency = <400>;
+ min-residency = <300>;
+ power-domains = <&pd_cores 0>,
+ <&pd_cores 1>,
+ <&pd_cores 2>,
+ <&pd_cores 3>,
+ <&pd_cores 4>,
+ <&pd_cores 5>,
+ <&pd_cores 6>,
+ <&pd_cores 7>;
+ };
+ };
+
+ STATE1: state1 {
+ compatible = "arm,cpu-idle-state";
+ index = <3>;
+ entry-method = "arm,psci-cpu-suspend";
+ psci-power-state = <0x1010000>;
+ entry-latency = <1000>;
+ exit-latency = <3000>;
+ min-residency = <6500>;
+ power-domains = <&pd_clusters 1>;
+ STATE1_0: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <2>;
+ entry-method = "arm,psci-cpu-suspend";
+ psci-power-state = <0x0010000>;
+ entry-latency = <200>;
+ exit-latency = <400>;
+ min-residency = <500>;
+ power-domains = <&pd_cores 8>,
+ <&pd_cores 9>,
+ <&pd_cores 10>,
+ <&pd_cores 11>,
+ <&pd_cores 12>,
+ <&pd_cores 13>,
+ <&pd_cores 14>,
+ <&pd_cores 15>;
+ };
+ };
+ };
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L1_0>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_0: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 0>;
+ };
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 0>;
+ };
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L1_1>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_1: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 1>;
+ };
+ };
+
+ CPU2: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_2>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_2: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 2>;
+ };
+ };
+
+ CPU3: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_3>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_3: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 3>;
+ };
+ };
+
+ CPU4: cpu at 10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L1_4>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_4: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 4>;
+ };
+ };
+
+ CPU5: cpu at 10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "psci";
+ next-level-cache = <&L1_5>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_5: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 5>;
+ };
+ };
+
+ CPU6: cpu at 10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_6>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_6: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 6>;
+ };
+ };
+
+ CPU7: cpu at 10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_7>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_7: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 7>;
+ };
+ };
+
+ CPU8: cpu at 100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L1_8>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_8: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 8>;
+ };
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 1>;
+ };
+ };
+
+ CPU9: cpu at 100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L1_9>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_9: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 9>;
+ };
+ };
+
+ CPU10: cpu at 100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_10>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_10: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 10>;
+ };
+ };
+
+ CPU11: cpu at 100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_11>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_11: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 11>;
+ };
+ };
+
+ CPU12: cpu at 100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L1_12>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_12: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 12>;
+ };
+ };
+
+ CPU13: cpu at 100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10001>;
+ enable-method = "psci";
+ next-level-cache = <&L1_13>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_13: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 13>;
+ };
+ };
+
+ CPU14: cpu at 100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_14>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_14: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 14>;
+ };
+ };
+
+ CPU15: cpu at 100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_15>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_15: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 15>;
+ };
+ };
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+pd_clusters: power-domain-clusters at 80002000 {
+ compatible = "arm,power-controller";
+ reg = <0x80002000 0x1000>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pd_cores: power-domain-cores at 80000000 {
+ compatible = "arm,power-controller";
+ reg = <0x80000000 0x1000>;
+ #power-domain-cells = <1>;
+ };
+};
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu-idle-states {
+
+ STATE0: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <3>;
+ entry-method = "psci";
+ psci-power-state = <0x1010000>;
+ entry-latency = <1000>;
+ exit-latency = <1500>;
+ min-residency = <1500>;
+ power-domains = <&pd_clusters 0>;
+ STATE0_1: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <2>;
+ entry-method = "psci";
+ psci-power-state = <0x0010000>;
+ entry-latency = <400>;
+ exit-latency = <500>;
+ min-residency = <300>;
+ power-domains = <&pd_cores 0>,
+ <&pd_cores 1>,
+ <&pd_cores 2>,
+ <&pd_cores 3>;
+ };
+ };
+
+ STATE1: state1 {
+ compatible = "arm,cpu-idle-state";
+ index = <3>;
+ entry-method = "psci";
+ psci-power-state = <0x1010000>;
+ entry-latency = <800>;
+ exit-latency = <2000>;
+ min-residency = <6500>;
+ power-domains = <&pd_clusters 1>;
+ STATE1_0: state0 {
+ compatible = "arm,cpu-idle-state";
+ index = <2>;
+ entry-method = "psci";
+ psci-power-state = <0x0010000>;
+ entry-latency = <300>;
+ exit-latency = <500>;
+ min-residency = <500>;
+ power-domains = <&pd_cores 4>,
+ <&pd_cores 5>,
+ <&pd_cores 6>,
+ <&pd_cores 7>;
+ };
+ };
+ };
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ next-level-cache = <&L1_0>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_0: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 0>;
+ };
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 0>;
+ };
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ next-level-cache = <&L1_1>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_1: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 1>;
+ };
+ };
+
+ CPU2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ next-level-cache = <&L1_2>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_2: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 2>;
+ };
+ };
+
+ CPU3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ next-level-cache = <&L1_3>;
+ cpu-idle-states = <&STATE0_1 &STATE0>;
+ L1_3: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 3>;
+ };
+ };
+
+ CPU4: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ next-level-cache = <&L1_4>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_4: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 4>;
+ };
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 1>;
+ };
+ };
+
+ CPU5: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ next-level-cache = <&L1_5>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_5: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 5>;
+ };
+ };
+
+ CPU6: cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ next-level-cache = <&L1_6>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_6: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 6>;
+ };
+ };
+
+ CPU7: cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ next-level-cache = <&L1_7>;
+ cpu-idle-states = <&STATE1_0 &STATE1>;
+ L1_7: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 7>;
+ };
+ };
+};
+
+===========================================
+4 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - power domain bindings
+ Documentation/devicetree/bindings/power/power_domain.txt
+
+[2] ARM Linux Kernel documentation - PSCI bindings
+ Documentation/devicetree/bindings/arm/psci.txt
+
+[3] ARM Server Base System Architecture (SBSA)
+ http://infocenter.arm.com/help/index.jsp
--
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