[PATCH v2 2/5] irqchip: gic: use writel instead of dsb + writel_relaxed

[Catalin Marinas]

On Mon, Feb 10, 2014 at 02:22:36PM +0000, Will Deacon wrote:
> When sending an SGI to another CPU, we require a DSB to ensure that
> any pending stores to normal memory are made visible to the recipient
> before the interrupt arrives.
> 
> Rather than use a vanilla dsb() (which will soon cause an assembly error
> on arm64) before the writel_relaxed, we can instead use dsb(ishst),
> since we just need to ensure that any pending normal writes are visible
> within the inner-shareable domain before we poke the GIC.
> 
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
> 
> v1 => v2: Use dsb ishst instead of writel (which requires an L2 sync)
>           since the sync should already have been executed by the caller
> 	  if required. We *might* be able to relax this further to a dmb
> 	  but Catalin and I haven't got to the bottom of that yet.

In the meantime,

Acked-by: Catalin Marinas <catalin.marinas at arm.com>