[PATCH 3/6] irqchip: gic: use writel instead of dsb + writel_relaxed
will.deacon at arm.com
Fri Feb 7 06:23:38 EST 2014
On Thu, Feb 06, 2014 at 03:20:48PM +0000, Catalin Marinas wrote:
> On Thu, Feb 06, 2014 at 01:26:44PM +0000, Will Deacon wrote:
> > On Thu, Feb 06, 2014 at 12:23:40PM +0000, Catalin Marinas wrote:
> > > On Thu, Feb 06, 2014 at 12:13:50PM +0000, Will Deacon wrote:
> > > > Ok, so if we assume that a dsb(ishst) is sufficient because the CPU we're
> > > > talking to is either (a) coherent in the inner-shareable domain or (b)
> > > > incoherent, and we flushed everything to PoC, then why wouldn't a dmb(ishst)
> > > > work?
> > >
> > > Because you want to guarantee the ordering between a store to Normal
> > > Cacheable memory vs store to Device for the IPI (see the mailbox example
> > > in the Barrier Litmus section ;)). The second is just a slave access, DMB
> > > guarantees observability from the master access perspective.
> > Ok, my reasoning is as follows:
> > - CPU0 tries to message CPU1. It writes to a location in normal memory,
> > then writes to the GICD to send the SGI
> > - We need to ensure that CPU1 observes the write to normal memory before
> > the write to GICD reaches the distributor. This is *not* about end-point
> > ordering (the usual non-coherent DMA example).
> > - A dmb ishst ensures that the two writes are observed in order by CPU1
> > (and, in fact, the inner-shareable domain containing CPU0).
> The last bullet point is not correct. DMB would only guarantee that the
> two writes (memory and GICD) are observed by CPU1 if CPU1 actually read
> the GICD (observability is defined for master accesses).
No, that's not how observability is defined, unfortunately.
Rather than attempt to solve this via email (your examples below are already
getting hard to follow :), how about we sit down with $drink_of_choice and
post back here with our conclusions?
In the meantime, I'll use dsb(ishst) because I think we now agree that
works. The question is whether it can be relaxed further to a dmb.
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