[PATCH v2 0/5] net: phy: Ethernet PHY powerdown optimization
f.fainelli at gmail.com
Tue Feb 4 17:51:27 EST 2014
2014-02-04 Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>:
> On 12/17/2013 08:43 PM, David Miller wrote:
>> From: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>> Date: Fri, 13 Dec 2013 10:20:24 +0100
>>> This is v2 of the ethernet PHY power optimization patches to reduce
>>> power consumption of network PHYs with link that are either unused or
>>> the corresponding netdev is down.
>>> Compared to the last version, this patch set drops a patch to disable
>>> unused PHYs after late initcall, as it is not compatible with a modular
>>> mdio bus . I'll investigate different ways to have a modular mdio bus
>>> driver get notified when driver loading is done.
>>> Again, a branch with v2 applied to v3.13-rc2 can also be found at
>>> https://github.com/shesselba/linux-dove.git topic/ethphy-power-v2
>>>  http://www.spinics.net/lists/arm-kernel/msg293028.html
>> Series applied, thanks.
> David, Mungunthan, Florian,
> as expected the above patches create a Linux to bootloader dependency
> that surfaces dumb bootloaders not initializing PHYs correctly.
> Andrew has a Kirkwood based board that does not power-up and restart
> auto-negotiation on the powered down PHY after a warm restart. While
> this specific bootloader allows a soft-workaround by issuing the
> required PHY writes before accessing the interface, others may not.
> I think we should allow the user to soft-disable the automatic
> power-down of PHYs, i.e. by exploiting a kernel parameter.
> Do you have any preference for naming it? My call would be something
> like libphy.suspend_halted = [0,1] with 1 being the default.
The name looks good to me, and it would avoid having to clear the
BMCR_PWRDOWN bit during the MDIO bus remove callback to workaround
BTW, it looks like we are omitting a 0.5 seconds delay after clearing
the BMCR_PWRDOWN bit:
220.127.116.11.5 Power Down
A PHY is not required to meet the RX_CLK and TX_CLK signal functional
requirements when either bit
0.11 or bit 0.10 is set to a logic one. A PHY shall meet the RX_CLK
and TX_CLK signal functional require-
ments defined in 22.2.2 within 0.5 s after both bit 0.11 and 0.10 are
cleared to zero."
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