[PATCH v2 1/1] net/macb: add TX multiqueue support for gem
cyrille.pitchen at atmel.com
Fri Dec 12 00:59:18 PST 2014
Le 12/12/2014 10:45, David Laight a écrit :
> From: Thomas Petazzoni
>> On Thu, 11 Dec 2014 11:16:51 +0100, Cyrille Pitchen wrote:
>>> +#define GEM_ISR1 0x0400
>>> +#define GEM_ISR2 0x0404
>>> +#define GEM_ISR3 0x0408
>>> +#define GEM_ISR4 0x040c
>>> +#define GEM_ISR5 0x0410
>>> +#define GEM_ISR6 0x0414
>>> +#define GEM_ISR7 0x0418
>> What about doing instead:
>> #define GEM_ISR(q) ((q) == 0 ? MACB_ISR : 0x400 + (q) << 2)
>> And ditto for all other registers, which will save a lot of boring repeated code.
> It will probably add a lot of object code and, depending on how often
> the registers are accesses, might have performance impact.
> #define GEM_ISR(n) (0x400 + (n) << 4)
> will save source code.
So you suggest that we keep the unsigned int fields ISR, IMR, IER, IDR, TBQP in
the struct macb_queue and initialize them once for all in macb_probe() like
patch v2 does but only replace the GEM_ISR1 .. GEM_ISR7 defines by GEM_ISR(n)
This way there would be to test at run time and we can handle the special
register mapping of queue0.
Is it what you meant?
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