[PATCH v3 11/16] clk: exynos5420: correct sysmmu-mfc parent clocks

[Alim Akhtar]

Hi Shaik,

On Thu, Apr 24, 2014 at 6:33 PM, Shaik Ameer Basha
<shaik.ameer at samsung.com> wrote:
> This patch corrects the wrong parent-child relationship
> between sysmmu-mfc clocks.
>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer at samsung.com>
> ---
Hoping you have tested vedio playback with this patch, especially
after across a suspend/resume cycles.
This looks ok.

Reviewed-by: Alim Akhtar <alim.akhtar at samsung.com>

>  drivers/clk/samsung/clk-exynos5420.c |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index d8fe6d8..6daf739 100755
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -82,6 +82,7 @@
>  #define SCLK_DIV_ISP0          0x10580
>  #define SCLK_DIV_ISP1          0x10584
>  #define DIV2_RATIO0            0x10590
> +#define DIV4_RATIO             0x105a0
>  #define GATE_BUS_TOP           0x10700
>  #define GATE_BUS_GEN           0x1073c
>  #define GATE_BUS_FSYS0         0x10740
> @@ -176,6 +177,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
>         SCLK_DIV_ISP0,
>         SCLK_DIV_ISP1,
>         DIV2_RATIO0,
> +       DIV4_RATIO,
>         GATE_BUS_TOP,
>         GATE_BUS_GEN,
>         GATE_BUS_FSYS0,
> @@ -636,6 +638,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
>         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
>
> +       /* Mfc Blk */
> +       DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
> +
>         /* GSCL Block */
>         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
>                 DIV2_RATIO0, 4, 2),
> @@ -873,8 +878,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>                         GATE_IP_DISP1, 8, 0, 0),
>
>         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
> -       GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
> -       GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
> +       GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
> +       GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
>
>         GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
>
> --
> 1.7.9.5
>
>
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-- 
Regards,
Alim