[PATCH] ARM: OMAP5: Redo THUMB mode switch on secondary CPU

Joel Fernandes joelf at ti.com
Tue Apr 29 19:53:47 PDT 2014

Here's a redo of the patch [1] that effectively does the same
thing but is the right way to do things by using ENDPROC instead.
The firmware correctly switches to THUMB before entry.

The patch applies ontop of the earlier patch [1].

[1] https://lkml.org/lkml/2014/4/22/1044

Suggested-by: Dave Martin <Dave.Martin at arm.com>
Cc: Dave Martin <Dave.Martin at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nishanth Menon <nm at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Joel Fernandes <joelf at ti.com>

Tony, the earlier patch went into your fixes, and can remain. This patch is just a simple redo of the same and can go in for v3.16, no problem. Thanks.

 arch/arm/mach-omap2/omap-headsmp.S |    6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 1809dce..bf36f26 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -31,10 +31,6 @@
  * register AuxCoreBoot0.
-THUMB( adr     r9, BSYM(wait)  )       @ CPU may be entered in ARM mode.
-THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
-THUMB( .thumb                  )       @ switch to Thumb now.
 wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
 	ldr	r0, [r2]
 	mov	r0, r0, lsr #5
@@ -43,7 +39,7 @@ wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
 	cmp	r0, r4
 	bne	wait
 	b	secondary_startup
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which

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