[PATCH] ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU

Joel Fernandes joelf at ti.com
Tue Apr 22 11:31:46 PDT 2014

On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control to
the kernel.  Switch to THUMB mode if required once the kernel is control of
secondary CPU. On OMAP4 on the other hand, it appears to be in THUMB mode on
entry so this is not required and SMP boot works as is.

Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Nishanth Menon <nm at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Joel Fernandes <joelf at ti.com>
 arch/arm/mach-omap2/omap-headsmp.S |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e9295..1809dce 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -1,7 +1,7 @@
  * Secondary CPU startup routine source file.
- * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2014 Texas Instruments, Inc.
  * Author:
  *      Santosh Shilimkar <santosh.shilimkar at ti.com>
@@ -28,9 +28,13 @@
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
  * The primary core will update this flag using a hardware
-+ * register AuxCoreBoot0.
+ * register AuxCoreBoot0.
+THUMB( adr     r9, BSYM(wait)  )       @ CPU may be entered in ARM mode.
+THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
+THUMB( .thumb                  )       @ switch to Thumb now.
 wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
 	ldr	r0, [r2]
 	mov	r0, r0, lsr #5

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