[PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver

[Vivek Gautam]

Hi Jingoo,


On Tue, Apr 22, 2014 at 7:48 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> On Wednesday, April 16, 2014 11:49 PM, Vivek Gautam wrote:
>> On Wed, Apr 16, 2014 at 7:14 PM, Tomasz Figa <t.figa at samsung.com> wrote:
>> > On 15.04.2014 08:09, Vivek Gautam wrote:
>> >> On Thu, Apr 10, 2014 at 5:09 PM, Vivek Gautam wrote:
>> >>> On Wed, Apr 9, 2014 at 7:03 PM, Tomasz Figa <t.figa at samsung.com> wrote:
>> >>>> On 09.04.2014 13:49, Vivek Gautam wrote:
>> >>>
>> >>> So, USB30_SCLK_100M is the SCLK that we are talking in the driver. I
>> >>> don't see any reference to XXTI in the USB 3.0 DRD controller chapter
>> >>> (in both Exynos5250 and 5420)
>> >>> In addition to this there's one more point to be noticed here.
>> >>> On Exynos5420 system, the sclk_usbphy300 (which is the sclk_usbphy30
>> >>> for USB DRD channel 0), is also the PICO phy clock, i.e. USB 2.0 phy
>> >>> clock.
>> >>> So we should add a similar clk_get() for this clock in the
>> >>> phy-exynos5250-usb2 driver too, to support Exynos5420.
>> >>
>> >>
>> >> Is something clear from the above block diagram ? (although the
>> >> diagram looks weird - space and tabs problem :-(  )
>> >> Basically there's the clock USB30_SCLK_100M which is going into the
>> >> USB 3.0 DRD PHY controller.
>> >> And this is the only sclk mentioned in the block diagram for USB 3.0
>> >> DRD controller in Exynos5420.
>> >> Same is not there in the block diagram in Exynos5250 UM.
>> >
>> >
>> > From what I can see in the documentation, there are 4 USB 3.0 related clocks
>> > generated in CMU:
>> >
>> >  - sclk_usbphy300,
>> >  - sclk_usbphy301,
>> >  - sclk_usbdrd300,
>> >  - sclk_usbdrd301,
>> >
>> > They are all rated to max. 24 MHz and the recommended operating frequency is
>> > 24 MHz, so it looks exactly like USB PHY reference, which is usually a 24
>> > MHz clock.
>> >
>> > To me, this looks like on Exynos5420 a separate special clock path is used
>> > instead of xusbxti as reference of USB 3.0 PHY and so the sclk should be
>> > simply passed as the "ref" clock.
>>
>> Ok, i will clear on this with the hardware engineer also once.
>> May be Jingoo can help me with this.
>>
>> Jingoo,
>> Can you please enquire about the clock path of usbphy30 reference
>> clocks on Exynos5420.
>> As mentioned by Tomasz above, we have sclk_usbphy300 and
>> sclk_usbphy301 as the reference clocks for USB3.0 DRD phy. *Also*
>> sclk_usbphy300 is used for Pico phy (which is the USb 2.0 phy used by
>> ehci/ohci controller on Exynos5420).
>> It will be of great help.
>
> Hi Vevek, Tomasz
>
> Long time no see.
>
> I asked USB S/W engineer and USB H/W engineer.
>
> There are two USB3.0 on Exynos5420; thus there are two sclks
> such as 'sclk_usbphy300 and sclk_usbphy301'.
>
> As Tomasz mentioned, 'sclk_usbphy300 and sclk_usbphy301' can
> be used instead of 'xusbxti' as reference of USB 3.0 PHY.

Thank you so much for getting this information.
I can re-spin the patch. :-)

>
> However, on Exynos5420, "ONLY" 'sclk_usbphy300' can be used
> for USB2.0 pico phy. (so, '301' CANNOT support USB2.0 pico phy.)

True, for USB 2.0 pico phy, only sclk_usbphy300 can be used.