[PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation

[Chen-Yu Tsai]

Hi,

On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
<boris.brezillon at free-electrons.com> wrote:
> Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
> sunxi clock documentation.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon at free-electrons.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index c2cb762..bc30387 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -25,6 +25,7 @@ Required properties:
>         "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
>         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
>         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
> +       "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s
                                                                       ^^^^
Copy paste error here.


ChenYu

>         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
>         "allwinner,sun4i-apb1-clk" - for the APB1 clock
>         "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing