[PATCH 2/3] ARM i.MX6: Fix ethernet PLL clocks

Dirk Behme dirk.behme at de.bosch.com
Wed Apr 9 00:11:34 PDT 2014

On 09.04.2014 08:59, Shawn Guo wrote:
> On Tue, Apr 08, 2014 at 01:44:06PM +0200, Dirk Behme wrote:
>> I'm no expert on this, but it seems to be able to use 100MHz or
>> 125Mhz enet clock, you additionally have to set the ENABLE_100M
>> bits. Which isn't done by above change,
> The following two lines added by the patch should just do.
> 	clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
> 	clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);

Many thanks, we'll test that :)

It seems that it's unsure at the moment if ENABLE_100M 
really needed, though ...

Many thanks and best regards


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