[PATCH 00/75] l2c series

Punnaiah Choudary Kalluri punnaiah.choudary.kalluri at xilinx.com
Mon Apr 7 08:52:08 PDT 2014

>On 04/07/2014 11:00 AM, Russell King - ARM Linux wrote:
>> On Mon, Apr 07, 2014 at 08:22:06AM +0200, Michal Simek wrote:
>>> On 04/04/2014 09:28 PM, Russell King - ARM Linux wrote:
>>>> On Fri, Apr 04, 2014 at 09:12:49AM +0200, Michal Simek wrote:
>>>>> On 04/03/2014 09:33 PM, Russell King - ARM Linux wrote:
>>>>>> On Thu, Apr 03, 2014 at 04:55:46PM +0200, Michal Simek wrote:
>>>>>>> Hi Russell,
>>>>>>> On 03/28/2014 04:12 PM, Russell King - ARM Linux wrote:
>>>>>>>> This is another posting of the L2 cache controller series.  I'm not
>>>>>>>> planning for this for the upcoming merge window, but the one after,
>>>>>>>> as people need to test it and still need to feed back to me on
>>>>>>>> various issues.  Hence, this is not a finalised series.
>>>> - a driver coupled to the arm,pl310-cache compatible for this which is
>>>>   distinctly separate from the main "driver" is probably a bad idea.
>>>>   what if we want our existing l2 stuff to couple into the driver model
>>>>   to expose some properties at a later date (eg, maybe to deal with
>>>>   stuff like the power management settings?)  For example, it may be
>>>>   that we want to expose the prefetch offset so that people can easily
>>>>   play with the value to determine the correct tuning for their workload.
>>> We choose that name for starting to discuss this how to do it better.
>>> We could use zynq-edac-l2 or zynq-edac-r3p2, etc version.
>> I'm not talking about the compatible name.  I'm certainly not suggesting
>> that you should describe the L2 as two separate devices in DT.  I'm saying
>> that this should appear as one _single_ driver for the entire device.
It means there are two drivers, one for l2 cache edac and one for l2 cache configuration
 and management in a single file. Please correct me if I am wrong.


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