Help for doubt about why update SCTLR by cr_alignment every syscall,IRQ,exception ?

Russell King - ARM Linux linux at
Sat Apr 5 02:43:13 PDT 2014

On Sat, Apr 05, 2014 at 01:41:17PM +0800, qixuan wu wrote:
> Dear King, all,

This code in arch/arm/kernel/head-common.S:

        bicne   r4, r0, #CR_A                   @ Clear 'A' bit
        stmneia r7, {r0, r4}                    @ Save control register values

saves different values to cr_alignment and cr_no_alignment.  One always
has the A bit cleared, the other may have the A bit set.

For ARMv5 and older, we must have the A bit set while in the kernel so
misaligned loads are aborted, so that they can be fixed up.  This
behaviour is relied upon by the networking code amongst other places.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

More information about the linux-arm-kernel mailing list