[PATCHv7 08/36] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
 arch/arm/boot/dts/omap443x.dtsi        |   20 +
 arch/arm/boot/dts/omap4460.dtsi        |   20 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   26 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1534 ++++++++++++++++++++++++++++++++
 5 files changed, 1617 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..a538a07
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..68464c5 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,24 @@
 		       0x4a00232C 0x4>;
 		compatible = "ti,omap4430-bandgap";
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap443x-clocks.dtsi"
+	};
+
+	clockdomains {
+		l3_init_clkdm: l3_init_clkdm {
+			compatible = "ti,clockdomain";
+			clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+		};
+
+		emu_sys_clkdm: emu_sys_clkdm {
+			compatible = "ti,clockdomain";
+			clocks = <&trace_clk_div_ck>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..f3c48d0 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,24 @@
 		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
 		gpios = <&gpio3 22 0>; /* tshut */
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap446x-clocks.dtsi"
+	};
+
+	clockdomains {
+		l3_init_clkdm: l3_init_clkdm {
+			compatible = "ti,clockdomain";
+			clocks = <&usb_host_fs_fck>, <&dpll_usb_ck>;
+		};
+
+		emu_sys_clkdm: emu_sys_clkdm {
+			compatible = "ti,clockdomain";
+			clocks = <&trace_clk_div_ck>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..96d5ddb
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a307888 0x4>;
+	ti,dividers = <8>, <16>, <32>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&div_ts_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..5644824
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1534 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&slimbus_src_clk>;
+	ti,bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4a306110 0x4>;
+	ti,index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a306108 0x4>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	reg = <0x4a30610c 0x4>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-m4xen-clock";
+	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	ti,max-div = <4>;
+	ti,index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&abe_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	ti,max-div = <2>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 4a00412c {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+	ti,bit-shift = <23>;
+	reg = <0x4a00412c 0x4>;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-clock";
+	clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck at 4a004140 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck at 4a00413c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a004100 0x4>;
+	ti,max-div = <2>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk at 4a0041dc {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a0041dc 0x4>;
+	ti,max-div = <4>;
+	ti,index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk at 4a00419c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a00419c 0x4>;
+	ti,max-div = <4>;
+	ti,index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck at 4a004138 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	ti,max-div = <31>;
+	ti,index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	reg-names = "gate-reg", "div-reg";
+	reg = <0x4a004134 0x4>, <0x4a004134 0x4>;
+	ti,gate-bit-shift = <8>;
+	ti,div-index-starts-at-one;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck at 4a004144 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck at 4a0041ac {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+	ti,bit-shift = <23>;
+	reg = <0x4a0041ac 0x4>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck at 4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck at 4a0041bc {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck at 4a00814c {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+	ti,bit-shift = <23>;
+	reg = <0x4a00814c 0x4>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	ti,max-div = <31>;
+	ti,index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	reg-names = "gate-reg", "div-reg";
+	reg = <0x4a008154 0x4>, <0x4a008154 0x4>;
+	ti,gate-bit-shift = <8>;
+	ti,div-index-starts-at-one;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck at 4a008160 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,max-div = <31>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-j-type-clock";
+	clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck at 4a0081b4 {
+	#clock-cells = <0>;
+	compatible = "ti,fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,clock-div = <1>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0081b4 0x4>;
+	ti,clock-mult = <1>;
+	ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,max-div = <127>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	ti,index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck at 4a008100 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+	reg = <0x4a008100 0x4>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	ti,dividers = <4>, <8>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	reg = <0x4a008108 0x4>;
+	ti,dividers = <2>, <4>;
+};
+
+func_96m_fclk: func_96m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	ti,dividers = <2>, <4>;
+};
+
+init_60m_fclk: init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	ti,dividers = <1>, <8>;
+};
+
+l3_div_ck: l3_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&div_core_ck>;
+	ti,bit-shift = <4>;
+	reg = <0x4a004100 0x4>;
+	ti,max-div = <2>;
+};
+
+l4_div_ck: l4_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a004100 0x4>;
+	ti,max-div = <2>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+	reg = <0x4a306108 0x4>;
+};
+
+mpu_periphclk: mpu_periphclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&aess_fclk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	ti,dividers = <2>, <1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4a008108 0x4>;
+	ti,max-div = <2>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck at 4a306100 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x4a306100 0x4>;
+	ti,max-div = <2>;
+};
+
+aes1_fck: aes1_fck at 4a0095a0 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck at 4a0095a8 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a004538 0x4>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&syc_clk_div_ck>;
+	ti,bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&extalt_clkin_ck>;
+	ti,bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll_per_m5x2_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_48mc_fclk>;
+	ti,bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	ti,bit-shift = <24>;
+	ti,max-div = <4>;
+	reg = <0x4a009028 0x4>;
+	ti,index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4a307838 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009460 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009468 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009470 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009478 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009480 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+};
+
+hsi_fck: hsi_fck at 4a009338 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	ti,bit-shift = <24>;
+	ti,max-div = <4>;
+	reg = <0x4a009338 0x4>;
+	ti,index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009020 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_96m_fclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a004540 0x4>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a004548 0x4>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a004550 0x4>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a004558 0x4>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+	ti,bit-shift = <25>;
+	reg = <0x4a0094e0 0x4>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a0094e0 0x4>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_48m_fclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck at 4a0095c8 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_24m_clk>;
+	ti,bit-shift = <9>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&abe_24m_fclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&pad_clks_ck>;
+	ti,bit-shift = <10>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&slimbus_clk>;
+	ti,bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_abe_24m_fclk>;
+	ti,bit-shift = <9>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_24mc_fclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&pad_slimbus_core_clks_ck>;
+	ti,bit-shift = <10>;
+	reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck at 4a008638 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck at 4a008630 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck at 4a008628 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	ti,bit-shift = <1>;
+	reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux at 4a307840 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a307840 0x4>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux at 4a009428 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009428 0x4>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux at 4a009430 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009430 0x4>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux at 4a009438 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009438 0x4>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux at 4a009440 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009440 0x4>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux at 4a009448 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009448 0x4>;
+};
+
+timer5_sync_mux: timer5_sync_mux at 4a004568 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+};
+
+timer6_sync_mux: timer6_sync_mux at 4a004570 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+};
+
+timer7_sync_mux: timer7_sync_mux at 4a004578 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+};
+
+timer8_sync_mux: timer8_sync_mux at 4a004580 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux at 4a009450 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009450 0x4>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_48mc_fclk>;
+	ti,bit-shift = <1>;
+	reg = <0x4a0093d0 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+	ti,bit-shift = <25>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	ti,bit-shift = <9>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <10>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	ti,bit-shift = <13>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <11>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <12>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	ti,bit-shift = <14>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&func_48mc_fclk>;
+	ti,bit-shift = <15>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <1>;
+	reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&otg_60m_gfclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_div_ck>;
+	ti,bit-shift = <0>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_32k_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <10>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <8>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&init_60m_fclk>;
+	ti,bit-shift = <9>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l4_div_ck>;
+	ti,bit-shift = <0>;
+	reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	ti,bit-shift = <24>;
+	reg = <0x4a307858 0x4>;
+	ti,dividers = <14>, <18>;
+};
+
+usim_fclk: usim_fclk at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&usim_ck>;
+	ti,bit-shift = <8>;
+	reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	ti,bit-shift = <20>;
+	reg = <0x4a307a20 0x4>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	ti,bit-shift = <22>;
+	reg = <0x4a307a20 0x4>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&pmd_stm_clock_mux_ck>;
+	ti,bit-shift = <27>;
+	ti,max-div = <64>;
+	reg = <0x4a307a20 0x4>;
+	ti,index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	ti,bit-shift = <24>;
+	reg = <0x4a307a20 0x4>;
+	ti,max-div = <64>;
+	ti,index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,clkdm-gate-clock";
+	clocks = <&trace_clk_div_div_ck>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a310 0x4>, <0x4a30a310 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk0_ck: auxclk0_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a310 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a314 0x4>, <0x4a30a314 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk1_ck: auxclk1_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a314 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a318 0x4>, <0x4a30a318 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk2_ck: auxclk2_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a318 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a31c 0x4>, <0x4a30a31c 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk3_ck: auxclk3_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a31c 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a320 0x4>, <0x4a30a320 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk4_ck: auxclk4_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a320 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "ti,no-wait-mux-gate-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	ti,gate-bit-shift = <8>;
+	reg = <0x4a30a324 0x4>, <0x4a30a324 0x4>;
+	ti,mux-bit-shift = <1>;
+	reg-names = "gate-reg", "mux-reg";
+};
+
+auxclk5_ck: auxclk5_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&auxclk5_src_ck>;
+	ti,bit-shift = <16>;
+	reg = <0x4a30a324 0x4>;
+	ti,max-div = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4a30a210 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a210 0x4>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4a30a214 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a214 0x4>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4a30a218 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a218 0x4>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4a30a21c {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a21c 0x4>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck at 4a30a220 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a220 0x4>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck at 4a30a224 {
+	#clock-cells = <0>;
+	compatible = "ti,mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	ti,bit-shift = <2>;
+	reg = <0x4a30a224 0x4>;
+};
+
+dummy_ck: dummy_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
\ No newline at end of file
-- 
1.7.9.5