[PATCH] clk: mxs: source LCD clock from PLL instead of from ref_xtal

[Fabio Estevam]

On Mon, Sep 23, 2013 at 4:50 AM, Hector Palacios
<hector.palacios at digi.com> wrote:
> The lcd clock hierarchy is as follows:
>
>     ref_clk (24MHz)-----\
>                          +--+ lcdif_sel (MUX type)
>     frac1_clk (480Mhz)--/   |
>                             \--+ lcdif_div (DIV type)
>                                |
>                                \-- lcdif (GATE type)
>
> The mxsfb driver retrieves the 'lcdif_div' clock from the DT, but the
> 'lcdif_sel' is by default sourced from 'ref_clk' which is a fixed 24MHz.
> This means the pixel clock can only be 24MHz or a power-of-two divisor
> of that frequency (12, 6, 3...) which is a very poor divisor granularity.
>
> Since the driver doesn't know about the different clocks that can
> source its clk parent from, we must select the PLL (480MHz) to be the
> parent during the general clocks initialization. This allows for much
> better divisor granularity and for more accurate frequencies for LCD
> displays.
>
> Signed-off-by: Hector Palacios <hector.palacios at digi.com>
> Tested-by: Fabio Estevam <fabio.estevam at freescale.com>
> CC: Maxime Rippard <maxime.ripard at free-electrons.com>
> CC: Marek Vasut <marex at denx.de>
> CC: Alexandre Belloni <alexandre.belloni at free-electrons.com>
> CC: Gwenhael Goavec-Merou <gwenhael.goavec-merou at armadeus.com>

You added a lot of people on Cc, but you missed the clk maintaner
(Mike Turquette) :-)