[PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
gautamvivek1987 at gmail.com
Wed Nov 20 03:57:23 EST 2013
On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I <kishon at ti.com> wrote:
sorry for the delayed response.
> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote:
>> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote:
>>> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han <jg1.han at samsung.com> wrote:
>>>> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block.
>>>> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block
>>>> and 2.0 block, respectively.
>>>> 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device
>>>> Base address: 0x1213 0000
>>>> 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device)
>>>> Base address: 0x1210 0000
>>>> 2.0 block(UTMI+) & 3.0 block(PIPE3)
>>> And this is of course the PHY used by DWC3 controller, which works at
>>> both High speed as well as Super Speed.
>>> Right ?
>> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+)
>> can be used for High speed.
> It should then come under *single IP muliple PHY* category similar to what
> Sylwester has done.
Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3
phy present in this PHY block ?
AFAICS the two phys (UTMI+ and PIPE3) do not really have separate
registers to program, and that's the reason
we program the entire PHY in a shot.
Samsung R&D Institute, Bangalore
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