[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Steffen Trumtrar]

On Tue, Nov 19, 2013 at 03:34:28PM -0600, Dinh Nguyen wrote:
> Hi Steffen,
> 
> On Tue, 2013-11-19 at 09:14 +0100, Steffen Trumtrar wrote:
> > Hi Dinh!
> > 
> > On Mon, Nov 18, 2013 at 11:11:52AM -0600, Dinh Nguyen wrote:
> > > Hi Steffen,
> > > 
> > > 
> > > On Tue, Nov 12, 2013 at 1:40 AM, Steffen Trumtrar <s.trumtrar at pengutronix.de
> > > > wrote:
> > > > I actually also wanted to change the l3_sp_clk, as it seems to be neglect
> > > > the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a
> > > > good
> > > > way without changing the binding or something. What do you thing about
> > > > that?
> > > > Is that wrong at the moment or do I miss something?
> > > >
> > > 
> > > Ah yes, the l3_sp_clk's parent should be l3_mp_clk and not mainclk.
> > > 
> > > Thanks for spotting that...
> > > 
> > > Dinh
> > > 
> > 
> > Hm, that doesn't sound right. Don't we currently have Gate+Divider combo in
> > the l3_mp_clk? If you turn off the clock gate from the l3_mp_clk, then l3_sp_clk
> > would also be turned off.
> > But according to Figure 2-3 in cv_5v4.pdf
> > 
> > 	DIV1 --------> GATE -----> L3_MP_CLK
> >                  |
> > 		 |---- DIV2 -----> L3_SP_CLK
> > 
> > So, l3_sp_clk's parent is the divider of l3_mp_clk but NOT the gate.
> 
> I just doubled checked. The L3_SP_CLK is taken before the gate of the
> L3_MP_CLK, so turning off the L3_MP_CLK does not turn off the L3_SP_CLK.
> So with this information, I think the parent for the L3_SP_CLK can be
> the L3_MP_CLK, so that the extra divider is accounted for.

Yes. Giving it another thought, you are right. That should be okay.

Thanks,
Steffen

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