[PATCH 2/5] ARM: dts: imx6sl: make pinctrl nodes board specific
Shawn Guo
shawn.guo at linaro.org
Mon Nov 4 09:45:30 EST 2013
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch provides a solution to avoid this device tree bloating problem
while still keeping boards share the common pinctrl setting data by
using DTC macro support. It creates <soc>-pingrp.h and move all those
pinctrl setting data into there as macro definitions. The <board>.dts
will instead define the pinctrl setting nodes that are necessary for the
board by referring to the macros in <soc>-pingrp.h, so that only the
pinctrl setting data that will be used by the board will get compiled
into the DTB for the board.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
arch/arm/boot/dts/imx6sl-evk.dts | 80 +++++++++++---
arch/arm/boot/dts/imx6sl-pingrp.h | 144 +++++++++++++++++++++++++
arch/arm/boot/dts/imx6sl.dtsi | 214 +------------------------------------
3 files changed, 211 insertions(+), 227 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index cc68e19..7d01c8e 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -45,7 +45,7 @@
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80 at 0 {
@@ -59,7 +59,7 @@
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec_1>;
+ pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "okay";
};
@@ -68,7 +68,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- hog {
+ imx6sl-evk {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
@@ -80,19 +80,71 @@
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
>;
};
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <MX6SL_FEC_PINGRP1>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX6SL_UART1_PINGRP1>;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <MX6SL_USBOTG1_PINGRP1>;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <MX6SL_USDHC1_PINGRP1>;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <MX6SL_USDHC1_PINGRP1_100MHZ>;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <MX6SL_USDHC1_PINGRP1_200MHZ>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX6SL_USDHC2_PINGRP1>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <MX6SL_USDHC2_PINGRP1_100MHZ>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <MX6SL_USDHC2_PINGRP1_200MHZ>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6SL_USDHC3_PINGRP1>;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <MX6SL_USDHC3_PINGRP1_100MHZ>;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <MX6SL_USDHC3_PINGRP1_200MHZ>;
+ };
};
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_1>;
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_1>;
+ pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
status = "okay";
};
@@ -106,9 +158,9 @@
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1_1>;
- pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio4 7 0>;
wp-gpios = <&gpio4 6 0>;
@@ -117,9 +169,9 @@
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2_1>;
- pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio5 0 0>;
wp-gpios = <&gpio4 29 0>;
status = "okay";
@@ -127,9 +179,9 @@
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio3 22 0>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6sl-pingrp.h b/arch/arm/boot/dts/imx6sl-pingrp.h
new file mode 100644
index 0000000..984077b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-pingrp.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SL_PINGRP_H
+#define __DTS_IMX6SL_PINGRP_H
+
+#define MX6SL_ECSPI1_PINGRP1 \
+ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 \
+ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 \
+ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
+
+#define MX6SL_FEC_PINGRP1 \
+ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 \
+ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 \
+ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 \
+ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 \
+ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 \
+ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 \
+ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 \
+ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 \
+ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+
+#define MX6SL_UART1_PINGRP1 \
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 \
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+
+#define MX6SL_USBOTG1_PINGRP1 \
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+
+#define MX6SL_USBOTG1_PINGRP2 \
+ MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
+
+#define MX6SL_USBOTG1_PINGRP3 \
+ MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
+
+#define MX6SL_USBOTG1_PINGRP4 \
+ MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
+
+#define MX6SL_USBOTG1_PINGRP5 \
+ MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
+
+#define MX6SL_USBOTG2_PINGRP1 \
+ MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
+
+#define MX6SL_USBOTG2_PINGRP2 \
+ MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
+
+#define MX6SL_USBOTG2_PINGRP3 \
+ MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
+
+#define MX6SL_USBOTG2_PINGRP4 \
+ MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
+
+#define MX6SL_USDHC1_PINGRP1 \
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 \
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 \
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 \
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 \
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 \
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 \
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 \
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 \
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 \
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+
+#define MX6SL_USDHC1_PINGRP1_100MHZ \
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 \
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 \
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 \
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 \
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 \
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 \
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 \
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 \
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 \
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+
+#define MX6SL_USDHC1_PINGRP1_200MHZ \
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 \
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 \
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 \
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 \
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 \
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 \
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 \
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 \
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 \
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
+
+#define MX6SL_USDHC2_PINGRP1 \
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 \
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 \
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 \
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 \
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 \
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+
+#define MX6SL_USDHC2_PINGRP1_100MHZ \
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 \
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 \
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 \
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 \
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 \
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+
+#define MX6SL_USDHC2_PINGRP1_200MHZ \
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 \
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 \
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 \
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 \
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 \
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+
+#define MX6SL_USDHC3_PINGRP1 \
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 \
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 \
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 \
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 \
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 \
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+
+#define MX6SL_USDHC3_PINGRP1_100MHZ \
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 \
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 \
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 \
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 \
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 \
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+
+#define MX6SL_USDHC3_PINGRP1_200MHZ \
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 \
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 \
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 \
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 \
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 \
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+
+#endif /* __DTS_IMX6SL_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 28558f1..000e1b4 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -9,6 +9,7 @@
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
+#include "imx6sl-pingrp.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
@@ -543,219 +544,6 @@
iomuxc: iomuxc at 020e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
-
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
- >;
- };
- };
-
- fec {
- pinctrl_fec_1: fecgrp-1 {
- fsl,pins = <
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
- >;
- };
- };
-
- uart1 {
- pinctrl_uart1_1: uart1grp-1 {
- fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
- >;
- };
- };
-
- usbotg1 {
- pinctrl_usbotg1_1: usbotg1grp-1 {
- fsl,pins = <
- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usbotg1_2: usbotg1grp-2 {
- fsl,pins = <
- MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usbotg1_3: usbotg1grp-3 {
- fsl,pins = <
- MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usbotg1_4: usbotg1grp-4 {
- fsl,pins = <
- MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usbotg1_5: usbotg1grp-5 {
- fsl,pins = <
- MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
- >;
- };
- };
-
- usbotg2 {
- pinctrl_usbotg2_1: usbotg2grp-1 {
- fsl,pins = <
- MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
- >;
- };
-
- pinctrl_usbotg2_2: usbotg2grp-2 {
- fsl,pins = <
- MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
- >;
- };
-
- pinctrl_usbotg2_3: usbotg2grp-3 {
- fsl,pins = <
- MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
- >;
- };
-
- pinctrl_usbotg2_4: usbotg2grp-4 {
- fsl,pins = <
- MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
- >;
- };
- };
-
- usdhc1 {
- pinctrl_usdhc1_1: usdhc1grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
- >;
- };
-
- pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
- >;
- };
-
-
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
- >;
- };
-
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
- >;
- };
- };
};
csi: csi at 020e4000 {
--
1.7.9.5
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