[PATCH 1/2] arm: correct GIC cpu interface range for Cortex A15/GIC 400

[Rob Herring]

On Fri, Nov 1, 2013 at 5:13 AM, Ian Campbell <ian.campbell at citrix.com> wrote:
> GICv2 (Cortex A15/GIC 400) have CPU interface registers up to offset 0x1004
> (the 32-bit GICC_DIR register a 0x1000). The GIC 400 documentation specifies
> the CPU interface region as being 0x2000 in size.
>
> Update all DTS entries claiming "arm,cortex-a15-gic" compatibility. Of these I
> only have personal experience with the vexpress a Calxeda (ecx) platforms and
> annecdotal evidence for omap and exynos. For the others I'm just assuming.
>
> Also update the example a15 binding in the documentation.
>
> The "Texas Instruments Keystone 2 SoC" platform which claim to have an a15
> compatible GIC but does not include the GICH/GICV registers. I've not touched
> that here.
>
> Signed-off-by: Ian Campbell <ian.campbell at citrix.com>
> Cc: devicetree at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org

Acked-by: Rob Herring <rob.herring at calxeda.com>