[PATCH v3 2/6] clk: samsung: Add support to register rate_table for PLL3xxx

[Doug Anderson]

Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan at linaro.org> wrote:
> From: Yadwinder Singh Brar <yadi.brar at samsung.com>
>
> This patch defines a common rate_table which will contain recommended p, m, s,
> k values for supported rates that needs to be changed for changing
> corresponding PLL's rate.
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c    |    8 ++++----
>  drivers/clk/samsung/clk-exynos5250.c |   14 +++++++-------
>  drivers/clk/samsung/clk-pll.c        |   14 ++++++++++++--
>  drivers/clk/samsung/clk-pll.h        |   35 ++++++++++++++++++++++++++++++++--
>  4 files changed, 56 insertions(+), 15 deletions(-)

This looks good to me.  Hopefully Tomasz agrees.  Tomasz: if you
haven't been following this thread, see
<https://patchwork.kernel.org/patch/2643351/> for how we resolved the
constant vs. calculated input clock.

Reviewed-by: Doug Anderson <dianders at chromium.org>