[PATCH 3/4] ARM: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead

[Gregory CLEMENT]

On 05/15/2013 05:41 PM, Will Deacon wrote:
> On Wed, May 15, 2013 at 04:36:43PM +0100, Gregory CLEMENT wrote:
>> On 05/15/2013 05:04 PM, Will Deacon wrote:
>>> On Wed, May 15, 2013 at 03:46:20PM +0100, Gregory CLEMENT wrote:
>>>> On 05/15/2013 04:06 PM, Will Deacon wrote:
>>>>> You could also try deleting both of the ALT_* lines and just putting a
>>>>> W(nop) in there directly.
>>>>
>>>> If I just delete the both of the ALT_* lines it no more hangs.
>>>> If I put a  W(nop) instead it hangs.
>>
>> It also hang with a simple nop by the way
> 
> Ok. Have you tried adding a different instruction (mov r0, r0, for example)?

it hanged again :(

I also try to boot a kernel in Thumb2, it doesn't hang in the same place but the kernel
crash latter

> 
>>>
>>> Wow. This doesn't sound good for your CPU and you might want to check with
>>> the Marvell guys...
>>>
>>> Extra things you could try:
>>>
>>> 	- Try adding a 16-bit nop instead (remove the W, build thumb-2 and
>>> 	  double check in your diasassembly)
>>>
>>> 	- Try adding the W(nop) to other places in the kernel and see if you
>>> 	  can tickle the lock-up elsewhere.
>>
>> I managed to add  W(nop) elsewhere in the kernel without getting any lock-up.
>>
>> Is the fact that this nop is the first instruction of the macro could have an
>> influence ?
> 
> I can't think why -- the macro is just expanded inline during assembly.

If I put anything before the "dcache_line_size r2, r3" line the kernel hang, but
just after it's ok.
> 
>>
>>>
>>> 	- Can you reproduce on the Armada XP? (since I have access to one of
>>> 	  those)
>>
>> No on Armada XP I don't have this kind of problem even on UP.
> 
> Is that compiling with CONFIG_SMP=n?
Yes

> 
> Will
> 
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-- 
Gregory Clement, Free Electrons
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development, consulting, training and support.
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