[PATCH] net/macb: fix ISR clear-on-write behavior only for some SoC

[Jean-Christophe PLAGNIOL-VILLARD]

On May 14, 2013, at 3:18 PM, Hein Tibosch <hein_tibosch at yahoo.es> wrote:

> 
> On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 08:58 Tue 14 May     , Hein Tibosch wrote:
>>> On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> On May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>>> 
>>>>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>>>>> introduces clear-on-write on ISR register. This behavior is not always
>>>>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>>>>> We are using a new Device Tree compatibility string and a capability
>>>>> property to actually activate this clear-on-write behavior on ISR.
>>>>> 
>>>>> Reported-by: Hein Tibosch <hein_tibosch at yahoo.es>
>>>>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>>>> can we detect it via the IP?
>>> This was my first proposal, have it based on the value of MACB's
>>> register 'MID' (offset 0x00fc, lower 16 bits).
>>> On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
>>> 
>>> So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
>>> equals to 0x00000119?
>> so no it will not work
>> 
>> as the gem on sama5 is 00020119
>> 
>> so version 0x119 too
>> 
>> nico
> 
> All right, that's a pity.
> 
> The only issue that remains then is the obligation to use CONFIG_OF,
> or:
> 
> +#if defined(CONFIG_OF)
> +	dev_id = of_match_device(macb_dt_ids, &pdev->dev);
> +	if (dev_id)
> +		bp->caps = (u32)dev_id->data;
> +
> +#endif
> 
> ?

no need as of_match_device is a inline of !OF

Best Regards,
J.
> 
> Hein
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