[PATCH V2 2/2] ARM/DTS/MVF600: add basic device tree source for Vybrid
Shawn Guo
shawn.guo at linaro.org
Sun May 5 22:38:10 EDT 2013
Generally, we use prefix "ARM: dts: ..." for arch/arm/dts and
"ARM: imx: ..." for arch/arm/mach-imx changes.
On Thu, May 02, 2013 at 03:38:05PM +0800, Jingchang Lu wrote:
> This patch adds basic device tree source for Freescale
> Vybrid Family MVF600 platform and Tower development board.
>
> Signed-off-by: Xiaochun Li <b41219 at freescale.com>
> Signed-off-by: Jingchang Lu <b35083 at freescale.com>
> ---
> V2:
> Add pinctrl support based on IMX new pinctrl framework
>
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/mvf600-pinfunc.h | 816 +++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/mvf600-twr.dts | 80 ++++
> arch/arm/boot/dts/mvf600.dtsi | 426 +++++++++++++++++++
> 4 files changed, 1324 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
> create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
> create mode 100644 arch/arm/boot/dts/mvf600.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8fd41b3..6402f21 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -119,7 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
> imx6q-sabreauto.dtb \
> imx6q-sabrelite.dtb \
> imx6q-sabresd.dtb \
> - imx6q-sbc6x.dtb
> + imx6q-sbc6x.dtb \
> + mvf600-twr.dtb
> dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
> imx23-olinuxino.dtb \
> imx23-stmp378x_devb.dtb \
> diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h
> new file mode 100644
> index 0000000..9fbc7a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-pinfunc.h
> @@ -0,0 +1,816 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DTS_MVF600_PINFUNC_H
> +#define __DTS_MVF600_PINFUNC_H
> +
> +/*
> + * Macro definations for MVF600 pin functions
> + *
> + * On Vybrid,pin's mux mode and pad control are in one 32-bit register.
> + * mux mode bits occupy bit[20:22] and pad config bits occupy bit[[0:15].
> + * So the config word is a combination of mux mode and control config value.
> + * imx common pinctrl driver requires a tuple of six elements to
> + * describe a pin. The tuple for MVF600 is as below:
> + * <mux_reg conf_reg input_reg mux_mode|conf_val input_val mux_mode|conf_val>
As I commented on the pinctrl driver, I prefer to define mvf600 pinfunc
ID as <mux_reg input_reg mux_mode input_val> and have pinctrl driver
handle the differences between mvf600 and imx.
> + */
...
> diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts
> new file mode 100644
> index 0000000..e2dafa2
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600-twr.dts
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +#include "mvf600.dtsi"
> +
> +/ {
> + model = "MVF600 Tower Board";
> + compatible = "fsl,mvf600-twr", "fsl,mvf600";
> +
> + chosen {
> + bootargs = "console=ttymxc1,115200";
> + };
> +
> + memory {
> + reg = <0x80000000 0x8000000>;
> + };
> +
> + clocks {
> + osc {
> + compatible = "fsl,mvf-osc", "fixed-clock";
Please drop the custom compatible for these fixed rate clocks, as we
will use common of_clk_init() to register them.
> + clock-frequency = <24000000>;
> + };
> +
> + audio_clk {
> + compatible = "fsl,mvf-audio-ext-clk", "fixed-clock";
> + clock-frequency = <24576000>;
> + };
> +
> + enet_clk {
> + compatible = "fsl,mvf-enet-ext-clk", "fixed-clock";
> + clock-frequency = <50000000>;
> + };
> + };
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1_1>;
> + status = "okay";
> +};
> +
> +&fec0 {
> + phy-mode = "rmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec0_1>;
> +};
Please sort the nodes in alphabet order of the labels, something like
the below.
&fec0 {
...
};
&fec1 {
...
};
&qspi00 {
...
};
&uart1 {
...
};
> +
> +&fec1 {
> + phy-mode = "rmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1_1>;
> +};
> +
> +
> +&qspi0 { /* QuadSPI0 */
> + fsl,spi-num-chipselects = <1>;
> + fsl,spi-flash-chipselects = <0>;
> + status = "okay";
> +
> + flash: s25fl128s at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spansion,s25fl128s";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + linux,modalias = "m25p80";
> + modal = "s25fl128s";
> + partition at 0 {
> + label = "s25fl128s";
> + reg = <0x0 0x1000000>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi
> new file mode 100644
> index 0000000..ca25f80
> --- /dev/null
> +++ b/arch/arm/boot/dts/mvf600.dtsi
> @@ -0,0 +1,426 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include "skeleton.dtsi"
> +#include "mvf600-pinfunc.h"
Put a blank line here.
> +/ {
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + };
> +
> +
Remove one blank line here.
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <0>;
If like imx that "osc" is a clock which is defined by SoC, the clock
should be put here rather than board dts.
> + };
> +
> +
One blank line is enough.
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&intc>;
> + ranges;
> +
> + aips0: aips-bus at 40000000 { /* AIPS0 */
With the label aips0 in front of, the comment "/* AIPS0 */" can just be
saved.
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&intc>;
> + reg = <0x40000000 0x70000>;
> + ranges;
> +
> + mscm: mscm at 40001000 {
> + compatible = "fsl,mvf-mscm";
We generally specify a particular hardware version by using given SoC
name in compatible. So in your case, "fsl,mvf600-mscm" is the one we
want to use.
> + reg = <0x40001000 0x1000>;
> + };
> +
> + intc: interrupt-controller at 40002000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-controller;
> + reg = <0x40003000 0x1000>,
> + <0x40002100 0x100>;
> + };
> +
> + L2: l2-cache at 40006000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x40006000 0x1000>;
> + interrupts = <0 6 0x04>;
> + cache-unified;
> + cache-level = <2>;
You may want the similar change as the patch below adds for imx6?
https://patchwork.kernel.org/patch/2491311/
> + };
> +
> + uart0: serial at 40027000 { /* UART0 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x40027000 0x1000>;
> + interrupts = <0 61 0x00>;
> + clocks = <&clks 39>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + uart1: serial at 40028000 { /* UART1 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x40028000 0x1000>;
> + interrupts = <0 62 0x04>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + uart2: serial at 40029000 { /* UART2 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x40029000 0x1000>;
> + interrupts = <0 63 0x04>;
> + clocks = <&clks 41>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + uart3: serial at 4002a000 { /* UART3 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x4002a000 0x1000>;
> + interrupts = <0 64 0x04>;
> + clocks = <&clks 42>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + pit:pit at 40037000 {
> + compatible = "fsl,mvf-pit";
> + reg = <0x40037000 0x1000>;
> + interrupts = <0 39 0x04>;
> + clock-names = "pit";
> + clocks = <&clks 45>;
> + };
> +
> + wdog at 4003e000 {
> + compatible = "fsl,mvf-wdt";
> + reg = <0x4003e000 0x1000>;
> + clock-names = "wdog";
> + clocks = <&clks 76>;
> + };
> +
> + qspi0: quadspi at 40044000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mvf-qspi";
> + reg = <0x40044000 0x1000>;
> + interrupts = <0 24 0x04>;
> + status = "disabled";
> + };
> +
> + iomuxc: iomuxc at 40048000 {
> + compatible = "fsl,mvf-iomuxc";
> + reg = <0x40048000 0x1000>;
> + #gpio-range-cells = <2>;
> +
> + /* functions and groups pins */
> + esdhc1 {
> + pinctrl_esdhc1_1: esdhc1grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTA24__ESDHC1_CLK(0x31ef)
> + MVF600_PAD_PTA25__ESDHC1_CMD(0x31ef)
> + MVF600_PAD_PTA26__ESDHC1_DAT0(0x31ef)
> + MVF600_PAD_PTA27__ESDHC1_DAT1(0x31ef)
> + MVF600_PAD_PTA28__ESDHC1_DATA2(0x31ef)
> + MVF600_PAD_PTA29__ESDHC1_DAT3(0x31ef)
> + MVF600_PAD_PTA7__GPIO_134(0x219d)
> + >;
> + };
> + };
Please sort all these iomuxc sub-nodes in alphabet sort of node name, so
that the new pinctrl entries can easily find their places.
Shawn
> +
> + i2c0 {
> + pinctrl_i2c0_1: i2c0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTB14__I2C0_SCL(0x30d3)
> + MVF600_PAD_PTB15__I2C0_SDA(0x30d3)
> + >;
> + };
> + };
> +
> + dspi0 {
> + pinctrl_dspi0_1: dspi0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTB19__DSPI0_CS0(0x1182)
> + MVF600_PAD_PTB20__DSPI0_SIN(0x1181)
> + MVF600_PAD_PTB21__DSPI0_SOUT(0x1182)
> + MVF600_PAD_PTB22__DSPI0_SCK(0x1182)
> + >;
> + };
> + };
> +
> + fec0 {
> + pinctrl_fec0_1: fec0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTA6__RMII_CLKIN(0x30d1)
> + MVF600_PAD_PTC0__ENET_RMII0_MDC(0x30d3)
> + MVF600_PAD_PTC1__ENET_RMII0_MDIO(0x30d1)
> + MVF600_PAD_PTC2__ENET_RMII0_CRS(0x30d1)
> + MVF600_PAD_PTC3__ENET_RMII0_RXD1(0x30d1)
> + MVF600_PAD_PTC4__ENET_RMII0_RXD0(0x30d1)
> + MVF600_PAD_PTC5__ENET_RMII0_RXER(0x30d1)
> + MVF600_PAD_PTC6__ENET_RMII0_TXD1(0x30d2)
> + MVF600_PAD_PTC7__ENET_RMII0_TXD0(0x30d2)
> + MVF600_PAD_PTC8__ENET_RMII0_TXEN(0x30d2)
> + >;
> + };
> + };
> +
> + fec1 {
> + pinctrl_fec1_1: fec1grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTC9__ENET_RMII1_MDC(0x30d2)
> + MVF600_PAD_PTC10__ENET_RMII1_MDIO(0x30d3)
> + MVF600_PAD_PTC11__ENET_RMII1_CRS(0x30d1)
> + MVF600_PAD_PTC12__ENET_RMII_RXD1(0x30d1)
> + MVF600_PAD_PTC13__ENET_RMII1_RXD0(0x30d1)
> + MVF600_PAD_PTC14__ENET_RMII1_RXER(0x30d1)
> + MVF600_PAD_PTC15__ENET_RMII1_TXD1(0x30d2)
> + MVF600_PAD_PTC16__ENET_RMII1_TXD0(0x30d2)
> + MVF600_PAD_PTC17__ENET_RMII1_TXEN(0x30d2)
> + >;
> + };
> + };
> +
> + sai2 {
> + pinctrl_sai2_1: sai2grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTA16__SAI2_TX_BCLK(0x02ed)
> + MVF600_PAD_PTA18__SAI2_TX_DATA(0x02ee)
> + MVF600_PAD_PTA19__SAI2_TX_SYNC(0x02ed)
> + MVF600_PAD_PTA21__SAI2_RX_BCLK(0x02ed)
> + MVF600_PAD_PTA22__SAI2_RX_DATA(0x02ed)
> + MVF600_PAD_PTA23__SAI2_RX_SYNC(0x02ed)
> + MVF600_PAD_PTB18__EXT_AUDIO_MCLK(0x02ed)
> + >;
> + };
> + };
> +
> + dcu0 {
> + pinctrl_dcu0_1: dcu0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTB8__GPIO_30(0x42)
> + MVF600_PAD_PTE0__DCU0_HSYNC(0x42)
> + MVF600_PAD_PTE1__DCU0_VSYNC(0x42)
> + MVF600_PAD_PTE2__DCU0_PCLK(0x42)
> + MVF600_PAD_PTE4__DCU0_DE(0x42)
> + MVF600_PAD_PTE5__DCU0_R0(0x42)
> + MVF600_PAD_PTE6__DCU0_R1(0x42)
> + MVF600_PAD_PTE7__DCU0_R2(0x42)
> + MVF600_PAD_PTE8__DCU0_R3(0x42)
> + MVF600_PAD_PTE9__DCU0_R4(0x42)
> + MVF600_PAD_PTE10__DCU0_R5(0x42)
> + MVF600_PAD_PTE11__DCU0_R6(0x42)
> + MVF600_PAD_PTE12__DCU0_R7(0x42)
> + MVF600_PAD_PTE13__DCU0_G0(0x42)
> + MVF600_PAD_PTE14__DCU0_G1(0x42)
> + MVF600_PAD_PTE15__DCU0_G2(0x42)
> + MVF600_PAD_PTE16__DCU0_G3(0x42)
> + MVF600_PAD_PTE17__DCU0_G4(0x42)
> + MVF600_PAD_PTE18__DCU0_G5(0x42)
> + MVF600_PAD_PTE19__DCU0_G6(0x42)
> + MVF600_PAD_PTE20__DCU0_G7(0x42)
> + MVF600_PAD_PTE21__DCU0_B0(0x42)
> + MVF600_PAD_PTE22__DCU0_B1(0x42)
> + MVF600_PAD_PTE23__DCU0_B2(0x42)
> + MVF600_PAD_PTE24__DCU0_B3(0x42)
> + MVF600_PAD_PTE25__DCU0_B4(0x42)
> + MVF600_PAD_PTE26__DCU0_B5(0x42)
> + MVF600_PAD_PTE27__DCU0_B6(0x42)
> + MVF600_PAD_PTE28__DCU0_B7(0x42)
> + >;
> + };
> + };
> +
> + uart1 {
> + pinctrl_uart1_1: uart1grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTB4__UART1_TX(0x21a2)
> + MVF600_PAD_PTB5__UART1_RX(0x21a1)
> + >;
> + };
> + };
> +
> + usbvbus {
> + pinctrl_usbvbus_1: usbvbusgrp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c)
> + MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c)
> + >;
> + };
> + };
> +
> + pwm0 {
> + pinctrl_pwm0_1: pwm0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTB0__FTM0_CH0(0x1582)
> + MVF600_PAD_PTB1__FTM0_CH1(0x1582)
> + MVF600_PAD_PTB2__FTM0_CH2(0x1582)
> + MVF600_PAD_PTB3__FTM0_CH3(0x1582)
> + MVF600_PAD_PTB6__FTM0_CH6(0x1582)
> + MVF600_PAD_PTB7__FTM0_CH7(0x1582)
> + >;
> + };
> + };
> +
> + qspi0 {
> + pinctrl_qspi0_1: qspi0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTD0__QSPI0_A_QSCK(0x307b)
> + MVF600_PAD_PTD1__QSPI0_A_CS0(0x307f)
> + MVF600_PAD_PTD2__QSPI0_A_DATA3(0x3073)
> + MVF600_PAD_PTD3__QSPI0_A_DATA2(0x3073)
> + MVF600_PAD_PTD4__QSPI0_A_DATA1(0x3073)
> + MVF600_PAD_PTD5__QSPI0_A_DATA0(0x307b)
> + MVF600_PAD_PTD7__QSPI0_B_QSCK(0x307b)
> + MVF600_PAD_PTD8__QSPI0_B_CS0(0x307f)
> + MVF600_PAD_PTD9__QSPI0_B_DATA3(0x3073)
> + MVF600_PAD_PTD10__QSPI0_B_DATA2(0x3073)
> + MVF600_PAD_PTD11__QSPI0_B_DATA1(0x3073)
> + MVF600_PAD_PTD12__QSPI0_B_DATA0(0x307b)
> + >;
> + };
> + };
> +
> + touchscreen0 {
> + pinctrl_ts0_1: ts0grp_1 {
> + fsl,pins = <
> + MVF600_PAD_PTA31__GPIO_21(0x219d)
> + >;
> + };
> + };
> +
> + };
> +
> + gpio1: gpio at 40049000 {
> + compatible = "fsl,mvf-gpio";
> + reg = <0x40049000 0x1000 0x400ff000 0x40>;
> + interrupts = <0 107 0x04>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&iomuxc 0 32>;
> + };
> +
> + gpio2: gpio at 4004a000 {
> + compatible = "fsl,mvf-gpio";
> + reg = <0x4004a000 0x1000 0x400ff040 0x40>;
> + interrupts = <0 108 0x04>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&iomuxc 32 32>;
> + };
> +
> + gpio3: gpio at 4004b000 {
> + compatible = "fsl,mvf-gpio";
> + reg = <0x4004b000 0x1000 0x400ff080 0x40>;
> + interrupts = <0 109 0x04>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&iomuxc 64 32>;
> + };
> +
> + gpio4: gpio at 4004c000 {
> + compatible = "fsl,mvf-gpio";
> + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
> + interrupts = <0 110 0x04>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&iomuxc 96 32>;
> + };
> +
> + gpio5: gpio at 4004d000 {
> + compatible = "fsl,mvf-gpio";
> + reg = <0x4004d000 0x1000 0x400ff100 0x40>;
> + interrupts = <0 111 0x04>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&iomuxc 128 7>;
> + };
> +
> + anatop at 40050000 {
> + compatible = "fsl,mvf-anatop";
> + reg = <0x40050000 0x1000>;
> + };
> +
> + clks: ccm at 4006b000 {
> + compatible = "fsl,mvf-ccm";
> + reg = <0x4006b000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + };
> +
> + aips1: aips-bus at 40080000 { /* AIPS1 */
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x40080000 0x80000>;
> + ranges;
> +
> + uart4: serial at 400a9000 { /* UART4 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x400a9000 0x1000>;
> + interrupts = <0 65 0x04>;
> + clocks = <&clks 43>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + uart5: serial at 400aa000 { /* UART5 */
> + compatible = "fsl,mvf-uart";
> + reg = <0x400aa000 0x1000>;
> + interrupts = <0 66 0x04>;
> + clocks = <&clks 44>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + fec0: ethernet at 400d0000 {
> + compatible = "fsl,mvf-fec";
> + reg = <0x400d0000 0x1000>;
> + interrupts = <0 78 0x04>;
> + clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> + clock-names = "ipg", "ahb", "ptp";
> + };
> +
> + fec1: ethernet at 400d1000 {
> + compatible = "fsl,mvf-fec";
> + reg = <0x400d1000 0x1000>;
> + interrupts = <0 79 0x04>;
> + clocks = <&clks 69>, <&clks 69>, <&clks 69>;
> + clock-names = "ipg", "ahb", "ptp";
> + };
> +
> + };
> + };
> +};
> --
> 1.8.0
>
>
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