[PATCHv2 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Mon, Mar 18, 2013 at 06:28:57PM +0000, Stephen Boyd wrote:
> From: Stepan Moskovchenko <stepanm at codeaurora.org>
> 
> Some early versions of the Krait CPU design incorrectly indicate
> that they only support the UDIV and SDIV instructions in Thumb
> mode when they actually support them in ARM and Thumb mode. It
> seems that these CPUs follow the DDI0406B ARM ARM which has two
> possible values for the divide instructions field, instead of the
> DDI0406C document which has three possible values.
> 
> Work around this problem by checking the MIDR against Krait CPUs
> with this faulty ISAR0 register and force the hwcaps to indicate
> support in both modes.
> 
> Cc: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Stepan Moskovchenko <stepanm at codeaurora.org>
> [sboyd: Rewrote commit text to reflect real reasoning now that
> 	we autodetect udiv/sdiv]
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---
>  arch/arm/mm/proc-v7.S | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Acked-by: Will Deacon <will.deacon at arm.com>

Will