[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon at arm.com>
>> Cc: Stepan Moskovchenko <stepanm at codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.

Ok. Care to ack the previous patch I sent then?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation