[PATCH 24/32] pci: PCIe driver for Marvell Armada 370/XP systems
wmb at firmworks.com
Sun Mar 10 14:33:08 EDT 2013
On 3/10/2013 5:06 AM, Thomas Petazzoni wrote:
> Dear Mitch Bradley,
> On Sat, 09 Mar 2013 19:04:51 -1000, Mitch Bradley wrote:
>> As stated in my recent reply to Jason, I thing the correct property is
>> "ranges". "Ranges" translates mappable child address space addresses
>> into parent addresses, and that is exactly what is going on. A specific
>> subset of config addresses is mappable into parent MMIO space.
> The PCI configuration space is *not* mapped in the MMIO space on
> Marvell hardware. In the MMIO space of each PCIe interface, there are
> many registers, only *two* of which are dedicated to accessing the PCI
> configuration space:
> * One register to set the offset in the PCI configuration space.
> * One register to read or write a value in the PCI configuration, at
> the offset specified in the first register.
> See the implementation of mvebu_pcie_hw_rd_conf() and
> mvebu_pcie_hw_wr_conf() in the driver.
> So really, the values specified in the reg = <...> property are *not*
> the PCI configuration spaces mapped in the MMIO space. They represent a
> bunch of per PCIe interface registers used to configure them, get the
> status of the link... and access, through an indirect mechanism, the
> PCI configuration space.
> Does this helps?
I agree that PCI config space accesses to *downstream* devices is via an
indirect-access register pair.
The question is, does that indirect-access mechanism apply also to the
internal config headers for the root port bridges?
According to section 20.15 of the MV78230 functional spec that I am
looking at, the configuration header registers are mapped to the
internal memory space. That section is unclear about whether those
registers are CPU-accessible via indirect-access config transactions.
When the PCIe hardware is configured for endpoint mode, the internal
headers can be accessed via PCIe config transactions from an external
port, but in root complex mode, the possibility of indirect access from
the CPU is not mentioned.
The manual is a little vague in some respects, but it does say quite
clearly that MMIO access to the root port bridge config header is
possible, and it lists the MMIO addresses thereof (section A.10).
So we all agree that access to external (downstream) config registers is
via the indirect register pair. The unclear thing is whether the
internal config registers for the root port bridges can be indirectly
Do we have empirical evidence that indirect-access works to the internal
root port bridge config headers?
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