[PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB

[Stephen Warren]

On 03/08/2013 07:00 AM, Laxman Dewangan wrote:
> UARTB clock bit in CAR register is 7. Correcting this
> in DTS file.

The register bit is 7, but the clock ID in the Tegra CAR DT binding is
96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and
2 separate IP block reset bits, or the other way around, so we highlight
the issue by assigning different clock IDs. See the comment before the
list of clock IDs in the binding document.