[V8 PATCH 01/16] usb: phy: mv_usb2: add PHY driver for marvell usb2 controller

[Felipe Balbi]

On Tue, Mar 05, 2013 at 11:43:35AM -0500, Alan Stern wrote:
> On Tue, 5 Mar 2013, Felipe Balbi wrote:
> 
> > Anyway, details are as follows:
> > 
> > readl() and writel() always add a memory barrier around each operation.
> 
> Is that supposed to be true on all architectures or only on ARM?

I believe it's true for every architecture which doesn't have strongly
ordered memory accesses. ARM is just one example of that ;-)

In any case, his read->set 1 bit->write loop isn't good even for
architectures with strongly ordered memory accesses. It will continue to
post unnecessary reads and writes to the interconnect.

-- 
balbi
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