Multi-platform, and secure-only ARM errata workarounds

Peter De Schrijver pdeschrijver at
Mon Mar 4 01:34:36 EST 2013

On Fri, Mar 01, 2013 at 06:37:27PM +0100, Stephen Warren wrote:


> Since some of the bits that enable WARs are banked per CPU, the WAR
> needs to be enabled by code running on each individual CPU, each time
> it's powered on. When a secure monitor exists, the CPU will boot through
> it (at least on Tegra, there is a single register that defines the boot
> vector for all CPUs; I don't know if that fact is ARM-architectural or
> not), so the secure monitor can apply the WAR if needed. However, when
> there is no secure monitor and the kernel runs in secure world, the
> kernel would have to apply those WARs, since the only code that runs is
> in the kernel.

The boot vector register is Tegra specific. At least on OMAP all cores boot
from ROM afaik.



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