[PATCH] clk: samsung: add set_rate and round_rate callbacks for pll45xx

[Yadwinder Singh Brar]

Hi Thomas,

>>> +     /* select a lookup table based on parent clock frequency */
>>> +     switch (*prate) {
>>> +     case 24000000:
>>> +             f = pll45xx_freq_lookup_24mhz;
>>> +             cnt = ARRAY_SIZE(pll45xx_freq_lookup_24mhz);
>>> +             break;
>>> +     default:
>>> +             pr_err("%s: unsupported parent clock rate", __func__);
>>> +             return *prate;
>>> +     }
>>
>> Again, PMS table can be set in register function and just used here.
>
> Ok, but it would be good to give another thought about having the
> lookup table tied to the pll configuration code. If required, we could
> have both options implemented. A pll will have a default PMS lookup
> table here and if a SoC specific table is needed, it can be supplied
> at the time of PLL registration.
>

I agree with this approach.
But I am not sure actually how many SoC can have common  table.

Regards,
Yadwinder