[PATCH V4 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Fri, Sep 21, 2012 at 09:46:10AM +0200, Gregory CLEMENT wrote:
>  arch/arm/include/asm/hardware/cache-aurora-l2.h |   55 ++++++

Will anything apart from cache-l2x0.c make use of this header file?
If not, it should be in arch/arm/mm.  I've said this many a time on
list that header files containing private definitions should be
co-located with their users.

Apart from that, and a few cosmetic additional unnecessary blank
lines, I think this is fine.  Relevant bits of the patch are below.

> +static unsigned long calc_range_end(unsigned long start, unsigned long end)
> +{
> +	/*
> +	 * Limit the number of cache lines processed at once,
> +	 * since cache range operations stall the CPU pipeline
> +	 * until completion.
> +	 */
> +
> +	if (end > start + MAX_RANGE_SIZE)
...
> +static void aurora_flush_range(unsigned long start, unsigned long end)
> +{
> +	if (!l2_wt_override) {
> +		start &= ~(CACHE_LINE_SIZE - 1);
> +		end = ALIGN(end, CACHE_LINE_SIZE);
> +		while (start != end) {
> +			unsigned long range_end = calc_range_end(start, end);
> +			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
> +					AURORA_FLUSH_RANGE_REG);
> +			start = range_end;
> +		}
> +	}
> +}
> +
> +
> +
>  static void l2x0_disable(void)
...
>  		if (data->setup)
>  			data->setup(np, &aux_val, &aux_mask);
> +
> +
> +		/* For aurora cache in no outer mode select the