[PATCH 1/7] ARM: hw_breakpoint: only clear OS lock when implemented on v7
will.deacon at arm.com
Thu Oct 25 10:49:30 EDT 2012
On Wed, Oct 24, 2012 at 11:53:29PM +0100, Stephen Boyd wrote:
> On 10/17/12 08:31, Will Deacon wrote:
> > The OS save and restore register are optional in debug architecture v7,
> > so check the status register before attempting to clear the OS lock.
> > Signed-off-by: Will Deacon <will.deacon at arm.com>
> Tested-by: Stephen Boyd <sboyd at codeaurora.org>
> > ---
> > arch/arm/kernel/hw_breakpoint.c | 10 +++++++++-
> > 1 files changed, 9 insertions(+), 1 deletions(-)
> > diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
> > index 281bf33..ec16ada 100644
> > --- a/arch/arm/kernel/hw_breakpoint.c
> > +++ b/arch/arm/kernel/hw_breakpoint.c
> > @@ -929,6 +929,13 @@ static void reset_ctrl_regs(void *unused)
> > asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
> > if ((dbg_power & 0x1) == 0)
> > err = -EPERM;
> > +
> > + /*
> > + * Check whether we implement OS save and restore.
> > + */
> > + asm volatile("mrc p14, 0, %0, c1, c1, 4" : "=r" (dbg_power));
> minor nit for this series. dbg_power has become a catch-all variable in
> this code. It would be nice if we named the variables used to hold the
> read register the same as the register or if we made the name of the
> variable generic like 'val'.
Thanks for your feedback and tested-bys on this series Stephen, I really
I'll send out a v2 and update the branch I'm sending to -next.
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