[alsa-devel] [PATCH v2 1/2] ARM: imx: clk: Split SSI clock into 'ipg' and 'per'

[Sascha Hauer]

On Tue, Oct 09, 2012 at 01:21:10AM -0300, Fabio Estevam wrote:
> Sascha,
> 
> On Mon, Oct 8, 2012 at 8:47 PM, Fabio Estevam <festevam at gmail.com> wrote:
> > Hi Sascha,
> >
> > On Mon, Oct 8, 2012 at 6:44 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >
> >> I am not sure it's good to work around that issue in the ssi driver. We
> >> could also just enable the clock in the clk driver as it seems to be a
> >> ccm related issue.
> >
> > Yes, it would be better if we could fix this in clk-imx27 instead, but
> > I was not able to provide such fix yet.
> 
> The ssi1_sel clock is defined as:
> 
> clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks,
> ARRAY_SIZE(ssi_sel_clks));
> 
> ,where ssi_sel_clks is:
> static const char *ssi_sel_clks[] = { "spll", "mpll", }
> 
> ,which matches with the mx27 reference manual.
> 
> How do we tell the clk api to select spll or mpll as the source for ssi_sel?
> 
> I understand how to do this from register level, but not from the api.

In the clk driver you can do a clk_set_parent(clk[ssi1_sel], clk[mpll]);

I wonder what the parent setting has to do with this problem. Could you
come up with a minimum patch to clk-imx27.c which fixes the problem?
Then we can discuss afterwards how to integrate it properly (or not the
least dirty).

Right now the clk framework has been succesful in turning the clk mess
into a proper tree. There currently is no API to manipulate that tree
in a non painful way. That would be the next steps.

Sascha

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