[PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode
Tony Lindgren
tony at atomide.com
Fri Oct 5 23:06:43 EDT 2012
* Nicolas Pitre <nicolas.pitre at linaro.org> [121005 18:33]:
> On Fri, 5 Oct 2012, Tony Lindgren wrote:
>
> > * Tony Lindgren <tony at atomide.com> [121005 16:27]:
> > > * Russell King - ARM Linux <linux at arm.linux.org.uk> [121005 16:10]:
> > > > On Fri, Oct 05, 2012 at 01:08:22PM -0700, Tony Lindgren wrote:
> > > > > Just bisected this down in linux-next for breaking booting of
> > > > > my omap2420 ARMv6 based n8x0..
> > > > >
> > > > > > --- a/arch/arm/kernel/head.S
> > > > > > +++ b/arch/arm/kernel/head.S
> > > > > > @@ -83,8 +83,12 @@ ENTRY(stext)
> > > > > > THUMB( .thumb ) @ switch to Thumb now.
> > > > > > THUMB(1: )
> > > > > >
> > > > > > - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
> > > > > > - @ and irqs disabled
> > > > > > +#ifdef CONFIG_ARM_VIRT_EXT
> > > > > > + bl __hyp_stub_install
> > > > > > +#endif
> > > > > > + @ ensure svc mode and all interrupts masked
> > > > > > + safe_svcmode_maskall r9
> > > > > > +
> > > > > > mrc p15, 0, r9, c0, c0 @ get processor id
> > > > > > bl __lookup_processor_type @ r5=procinfo r9=cpuid
> > > > > > movs r10, r5 @ invalid processor (r5=0)?
> > > > >
> > > > > ..and looks like undoing this part fixes it. Any ideas?
> > > > >
> > > > > I quickly tried disabling ARCH_OMAP3 and ARCH_OMAP4 so it's
> > > > > ARMv6 but that does not help.
> >
> > The same kernel boots on 2430sdp, which is the same ARMv6 core
> > as 2430 if I remember correctly. So this hints that it has something
> > to do with the bits set differently by the bootloader?
>
> Possibly.
>
> What if you apply this on top:
>
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index 683a1e6b60..b276c26e19 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -254,8 +254,7 @@
> mov lr , \reg
> and lr , lr , #MODE_MASK
> cmp lr , #HYP_MODE
> - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
> - bic \reg , \reg , #MODE_MASK
> + mov \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
> orr \reg , \reg , #SVC_MODE
> THUMB( orr \reg , \reg , #PSR_T_BIT )
> msr spsr_cxsf, \reg
>
>
>
Thanks but that does not seem to help.
Regards,
Tony
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