[PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ

[Etienne CARRIERE ST]

> Tue 11-13-2012 8:23 PM
> From: Abhimanyu Kapur <abhimanyu.kapur at outlook.com>
>
> > Secure code in TrustZone space may need to perform L2 cache
> > maintenance operations. A shared mutex is required to synchronize
> > linux l2cc maintenance and TZ l2cc maintenance.
> 
> If you are using PL310 with thrustzone support then the L2 cache lines 
> are secure bit tagged ; your design should be such that the secure (TZ) 
> side only does operations on secure cache lines and non-secure side 
> does operations only on non-secure cache lines. So each entity (TZ 
> and nonTZ) if maintains their own cache and ensures integrity before 
> switching over via monitor, this might not be needed.

I don't think 2 cores can safely write the LX20_CLEAN/INV_LINE_PA registers of the PL310 at the same time, even if targeting different lines.
Each core TZ code must protect against other core (being UnSecure or TZ mode). The core IRQ disabling is required to protect from deadlock nonTZ and TZ worlds.

Regards,
etienne