[PATCH] arm: zynq: add system level control register manager

Daniel Borkmann danborkmann at iogearbox.net
Tue Nov 13 14:25:21 EST 2012


On Tue, Nov 13, 2012 at 7:37 PM, Josh Cartwright <josh.cartwright at ni.com> wrote:
> On Fri, Nov 09, 2012 at 10:49:07AM +0100, Daniel Borkmann wrote:
>> On Thu, Nov 8, 2012 at 5:01 PM, Josh Cartwright <joshc at eso.teric.us> wrote:
>> > On Wed, Oct 31, 2012 at 07:36:12PM +0100, Daniel Borkmann wrote:
>> >> This patch for the Xilinx Zynq ARM architecture adds management of system
>> >> level control register. The code is taken from the Xilinx-internal Linux
>> >> Git tree and cleaned up a bit for mainline integration. Besides others,
>> >> this patch is needed in order to integrate further drivers for Zynq such as
>> >> the Zynq xemacps networking device driver. The patch is aganst the latest
>> >> arm-soc tree.
>> >>
>> >> Signed-off-by: Daniel Borkmann <daniel.borkmann at tik.ee.ethz.ch>
>> >> Cc: Michal Simek <michals at xilinx.com>
>> >> Cc: John Linn <john.linn at xilinx.com>
>> >> Cc: Arnd Bergmann <arnd at arndb.de>
>> >> ---
>> >
>> > These changes will conflict with my pending clk patchset [1], as I'm
>> > introducing bindings for the SLCR (and its clk interfaces).
>>
>> Oops, okay. Then your's has priority, of course.
>
> I did not mean to discourage.  I just meant to say that we should work
> out how this work can be done on top of the clk changes.
>
>> > It seems like a hefty chunk of the out-of-tree slcr driver is related to
>> > configuring MIO.  I think it would be really nice if this driver was
>> > reworked to use the pinctrl subsystem, and also to provide suitable
>> > device tree bindings.
>>
>> Agreed. If there's a chance to help with further Zynq integration and
>> to develop this driver with testing on Qemu for ARM Zynq, I'd like to
>> give it a try. (The board is a bit expensive as a hobby only.)
>
> My concern is that, especially regarding the configuration of MIO, being
> able to do adequate testing will require real hardware.  It isn't clear
> to me what the state of qemu's slcr/mio model is.

I added Peter Crosthwaite into CC, since he could provide an answer to
that (I've been told).



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