[PATCH] ARM: implement optimized percpu variable access

[Will Deacon]

On Mon, Nov 12, 2012 at 02:21:27PM +0000, Rob Herring wrote:
> On 11/12/2012 04:23 AM, Will Deacon wrote:
> > Hi Rob,
> > 
> > On Sun, Nov 11, 2012 at 03:20:40AM +0000, Rob Herring wrote:
> >> From: Rob Herring <rob.herring at calxeda.com>
> >>
> >> Use the previously unused TPIDRPRW register to store percpu offsets.
> >> TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.
> >>
> >> This saves 2 loads for each percpu variable access which should yield
> >> improved performance, but the improvement has not been quantified.
> > 
> > The patch looks largely fine to me (one minor comment below), but we should
> > try and see what the performance difference is like on a few cores before
> > merging this. Have you tried something like hackbench to see if the
> > difference is measurable there? If not, I guess we'll need something more
> > targetted.
> 
> Looks like it's about a 1.4% improvement on Cortex-A9 (highbank) with
> hackbench.
> 
> Average of 30 runs of "hackbench -l 1000":
> 
> Before: 6.2190666667
> After: 6.1347666667
> 
> I'll add this data to the commit msg.

Wow, that's really cool! I'll take it for a spin on 11MPCore to test the v6
angle...

Will