[PATCH 13/15] ARM: DTS: AM33XX: Add nodes for OCMCRAM and Mailbox

Bedia, Vaibhav vaibhav.bedia at ti.com
Mon Nov 5 12:57:54 EST 2012


On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
[...]
> >
> On OMAP the OCMC RAM is always clocked and doesn't need any special
> clock enable. CM_L3_2_OCMC_RAM_CLKCTRL module mode field is read only.
> Isn't it same on AMXX ?
> 

On AM33xx, OCMC RAM is in PER domain and the corresponding CLKCLTR module
mode fields are r/w. OCMC RAM needs to be disabled as part of the DeepSleep0
entry to let PER domain transition.

Regards,
Vaibhav 




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