[PATCH V2] ARM: OMAP3+: PM: VP: ensure VP is idle before disable
Menon, Nishanth
nm at ti.com
Mon May 21 11:14:30 EDT 2012
On Mon, May 21, 2012 at 9:51 AM, Eduardo Valentin
<eduardo.valentin at ti.com> wrote:
>
>
> On Mon, May 21, 2012 at 08:36:35AM -0500, ext Nishanth Menon wrote:
>> Sat, May 19, 2012 at 4:52 AM, Eduardo Valentin <eduardo.valentin at ti.com>
>> wrote:
>> >
>> >
>> > I guess it is time to properly document this increasing busy loop delay..
>> > As it is getting closer to ms scale..
>> Does the following sound good?
>> /* Maximum time for Voltage Processor to enter or exit idle */
>
> Sounds way better :-). If you have an estimation of how long it takes
> in the average case, it might help. But I am OK already with the above,
> in case you don't have the estimation.
/*
* Maximum time for Voltage Processor to enter or exit idle
* worst case is around 100uSec depending on when we intercepted VP
* we use 5 times worst case value to be sure that the system flags
* invalid condition
*/
better?
Regards,
Nishanth Menon
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