On Fri, 27 Apr 2012, Rajendra Nayak wrote: > The register bits for MPU_CLK_SRC and IVA2_CLK_SRC > in CM_CLKSEL1_PLL register are 3 bits wide. > Fix the MASK definition accordingly. > > Signed-off-by: Rajendra Nayak <rnayak at ti.com> Thanks, queued for 3.5. - Paul