[PATCH v4] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC
gregory.clement at free-electrons.com
Tue Jun 26 04:28:24 EDT 2012
You'll find in this patch set the third version of the initial support
for a new family of ARMv7-compatible Marvell SoCs.
As for the previous releases, both the Armada 370 and the Armada XP
SoCs are supported in this directory, and we are able to build a
single kernel image that boots on both SoCs. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set. We are currently using Marvell evaluation boards for
both of those SoCs, and the support for those boards is added in this
We remained focused on a limited preliminary support which only
includes the necessary code for timer and IRQ support, the serial
controller is a standard 16550-compatible one. The diffstat looks
Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt | 23 +
Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt | 11 +
Documentation/devicetree/bindings/arm/armada-370-xp.txt | 24 +
Documentation/devicetree/bindings/arm/mvebu-system-controller.txt | 16 +
MAINTAINERS | 8 +
arch/arm/Kconfig | 14 +
arch/arm/Makefile | 1 +
arch/arm/boot/dts/armada-370-db.dts | 42 +
arch/arm/boot/dts/armada-370-xp.dtsi | 68 ++
arch/arm/boot/dts/armada-370.dtsi | 35 +
arch/arm/boot/dts/armada-xp-db.dts | 50 +
arch/arm/boot/dts/armada-xp.dtsi | 55 +
arch/arm/configs/mvebu_defconfig | 46 +
arch/arm/mach-mvebu/Kconfig | 16 +
arch/arm/mach-mvebu/Makefile | 2 +
arch/arm/mach-mvebu/Makefile.boot | 1 +
arch/arm/mach-mvebu/armada-370-xp.c | 63 ++
arch/arm/mach-mvebu/common.h | 23 +
arch/arm/mach-mvebu/include/mach/armada-370-xp.h | 22 +
arch/arm/mach-mvebu/include/mach/debug-macro.S | 24 +
arch/arm/mach-mvebu/include/mach/timex.h | 13 +
arch/arm/mach-mvebu/include/mach/uncompress.h | 43 +
arch/arm/mach-mvebu/irq-armada-370-xp.c | 133 +++
arch/arm/mach-mvebu/system-controller.c | 105 ++
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 3 +-
drivers/clocksource/time-armada-370-xp.c | 242 +++++
include/linux/time-armada-370-xp.h | 18 +
28 files changed, 1103 insertions(+), 1 deletion(-)
This patch set, and the support for those SoCs, started as a
collaborative effort from Marvell engineers (who have done the initial
development work) and Free Electrons engineers (who are reshaping the
code for mainline submission, adding device tree support, etc.). This
effort has also received contributions from Ben Dooks from Codethink.
The patch set is based on your arm-soc/for-next branch (updated on Monday
Do you think this patch set has a chance of hitting the 3.6 merge
We are willing to quickly resubmit updated versions to take into
account new comments. We have a lot more code to support those new
SoCs, and we would like to make progress in submitting those other
parts for the mainline.
Changes between v3 and v4:
* If the system controller device is not found during initialization,
no more warnings are issued and the function doesn't fail.
* The system controller driver becomes more generic to handle the
other mvebu SoCs. Inside the device tree it is now called either
armada-370-xp-system-controller or mvebu-other-system-controller.
Then depending of the compatibility name the driver selects the
accurate offset and bit mask. The way to handle different variants
of the same controller was inspired by the of_serial.c file.
* A documentation was added for the "system-controller" binding
* The "select CPU_V7" was moved from ARCH_MVEBU in arch/arm/Kconfig
to MACH_ARMADA_370_XP in arch/arm/mach-mvebu/Kconfig. Thanks to this
the other mvebu" machines will be able to use CPU_V5
* Some armada_370_xp strings have been renamed to armada-370-xp to
keep the coherency with other parts of the code.
Changes between v2 and v3:
* The timer support code has been moved to drivers/clocksource/ and
the necessary related changes have been made
* There is now a minimal "system-controller" driver that gets
instantiated through DT entries. This driver allows to expose the
features made available through a set of miscellaneous registers
that do not belong to any specific device in the SoC. For the
moment, we only use it to implement the .restart() hook.
* The defconfig has been changed to allow the support for up to four
8250-compatible serial ports, since Armada XP has four such
ports. The DTS file has been modified to enable those four ports,
and they have all been tested successfully on the Armada XP DB
* Moved the "arm: mach-mvebu: add compilation/configuration change"
patch towards the end of the patch set
* Marked the "serial" device as "disabled" in the .dtsi file, and
enable the ones that are actually used in the board specific .dts
* Dropped the _dt suffix as the device tree support is implicit now.
* Don't use anymore a MVEBU_REGS_PHYS_BASE define and reintroduce a
Changes between v1 and v2:
* Use the mach-mvebu directory as suggested on the mailing-list. So
far, this directory only contains the support for Armada 370/XP,
but the plan is that it should ultimately contain the support for
all other SoCs produced by the Marvell Engineering Business Unit.
* Converted most the "armada" word by the "mvebu", but as some code
remains specific to the Armada 370 and Armada XP SOC, then created
also the aramada_370_xp suffix for this part. This suffix was
dedicated for the irq and timer part. It was also used for the
register related to the reset part. And of course it was also used
for the device tree part.
* Merged axp-dt.c and a370-dt.c files in one single
* Deleted most of the mapping address in include/mach/armada.h and
split it in two headers file:
- mvebu.h which contains the virtual and physical mapping for the
internal registers of the mvebu SOC. This ones are mainly used for
the early print during boot.
- armada_370_xp which contains the registers offset and mask for
resetting the CPU.
* Removed unused headers such as
- hardware.h by directly including accurate header when needed
- gpio.h by removing the dependencies to PLAT-ORION
- io.h no more needed for CPI
- irqs.h by using SPARSE_IRQ
- system.h no more needed for new SOC
* Removed the PCI related code as it was not necessary for the
* Removed all the PLAT-ORION dependencies remaining
* Ensured property reading checks for error when getting data from
device tree in the timer file. This was a patch from Ben Dooks with
the following comments:
"The call to of_property_read_u32() only checks for the value that
the clk variable is set to being non-zero, and not the return value
of the call itself.
This caused a system without the clock-frequency attribute to fail
to boot as it used a random value on the stack to setup the system
timers and thus cause an interrupt storm.
Also ensure clk is set to zero, to avoid warnings."
* Converted irq controller code to use SPARSE_IRQ
* Added the following bug fixes and improvements in irq.c from Ben
- MPIC: BUG_ON() if the of_iomap() fails: Ensure that if either
resource is missing, we stop the kernel in a reasonably fatal way.
- MPIC: Move main register base to base of MPIC registers: The
current kernel driver had the MPIC base at the base of the block
containing the MPIC and not the MPIC itself. Change this value in
the driver and the .dtsi file
Also change the register size in the .dtsi to be the size of the
register range for the MIPC and not the block it is in.
- MPIC: Move per-cpu register base: The current kernel driver had
the MPIC per-cpu register base at the base of the per-cpu register
block and not at the base of the specific per-cpu interrupt
Move the driver and .dtsi to use the correct base and size.
- MPIC: number fetch should use irqd_to_hwirq(): The mask and unmask
routines are assuming that d->irq is a 1:1 mapping with the
interrupt hardware. Use the irqd_to_hwirq() call to map the
irq_data to the hardware irq number directly.
- MPIC: read number of interrupts from control register: Read the
number of MPIC interrupts from the controller and only register
More information about the linux-arm-kernel