[PATCH V2] clk: give clock chance to change parent at setrate stage

[Mike Turquette]

On 20120516-19:55, zhoujie wu wrote:
> If I separate this clock to mux->divider model,
> mux node will NOT set CLK_SET_RATE_PARENT flag
> divider node will set CLK_SET_RATE_PARENT flag
> 
> When I want to change this clock's rate, it will at first find proper
> divider with current parent rate,
> if best_parent_rate != cur_parent_rate, this means we should re-parent
> the mux. The mux node rate
> will be change at first, and then divider. Per your suggestion, in mux
> .set_rate ops we disable new parent
> and set mux field, then disable old parent.
> But there is a limitation here,  write to the mux filed doesn't really
> change the source of the parent. It requires
> the trigger bits to be set.
> If we don't set trigger bits here, the source is still not change, we
> could not disable old parent. Where is the proper place to disable it?
> If we set mux and trigger here, we may use some tmp dangerous clock
> rate since divider has not update yet.
> For example, rate 400M = mux_400M/ div_1 at first. When we want to set
> to 533M, we have change mux to 1066M here, we may get tmp rate 1066M =
> 1066M/1, but this clock may not run up to 1066M.
> That is why we think it is more safe to set mux&div&trigger the same time.

Hi Zhoujie Wu,

I still think that the separate clock nodes could work for you.  I don't
know if you have actually tried to implement them or not.

Regardless I want you to know that I've changed my mind about your
original patch to give clk_set_rate the option to select a new parent.
I think that this behavior is necessary for a variety of reasons
(locking correctness amongst other things).  I'm going to implement it
differently than your patch does, but it should help you out.

I'll Cc you on the patch when it hits the list.

Regards,
Mike