[PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes

[Will Deacon]

Hi Stephen,

On Mon, Jan 16, 2012 at 06:22:34PM +0000, Stephen Boyd wrote:
> On 01/16/12 07:44, Will Deacon wrote:
> > The linker script assumes a cacheline size of 32 bytes when aligning
> > the .data..cacheline_aligned and .data..percpu sections.
> >
> > This patch updates the script to use L1_CACHE_BYTES, which should be set
> > to 64 on platforms that require it.
> >
> > Signed-off-by: Will Deacon <will.deacon at arm.com>
> > ---
> >
> > v2: incorporated suggestions from Stephen Boyd
> 
> What do you think about aligning the exception fixup table to the same
> value?

Hmm, I'm not sure I see what that gains us over the current 32-byte
alignment. Are you seeing any measurable performance difference with it being
cacheline-aligned?

Will