MX28 fec clock frequency
Peter Rusko
rusko.peter at prolan.hu
Tue Jan 10 10:39:37 EST 2012
On 2012-01-10 15:00, Shawn Guo wrote:
> Another point worth checking is bit field ATIME_INC of register
> HW_ENET_MAC_ATIME_INC. It should be 25 if your CLK_ENET_TIME runs
> at 40 MHz.
>
No, that was set correctly. Finally, I've found my mistake. I've
overwritten the other bits when writing the divider so xtal clock was
selected automatically.
Silly little mistake, isn't it? :) Anyway, thank you for your help.
--
Ruskó Péter
Fejlesztőmérnök
Prolan Zrt. / Prolan Co.
Hungary 2011 Budakalász, Szentendrei út 1-3.
Tel./Phone: +36 20 954 3118
Fax: +36 26 540 420
E-mail: rusko.peter at prolan.hu
Web: www.prolan.hu
Timezone:CET
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