MX28 fec clock frequency

[Shawn Guo]

On Tue, Jan 10, 2012 at 02:08:31PM +0100, Peter Rusko wrote:
> >I'm not sure it's causing the problem you are seeing.  But from i.MX28
> >spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
> >be polled for new divider setting?
> >
> 
> Thank you, I've added the check, but unfortunately it didn't help :(
> 
Another point worth checking is bit field ATIME_INC of register
HW_ENET_MAC_ATIME_INC.  It should be 25 if your CLK_ENET_TIME runs
at 40 MHz.

-- 
Regards,
Shawn