MX28 fec clock frequency

[Shawn Guo]

On Mon, Jan 09, 2012 at 03:07:44PM +0100, Peter Rusko wrote:
> +	/* ENET_CLK setup */
> +	enet_clk.set_parent(&enet_clk, &pll0_clk);
> +	__raw_writel(BF_CLKCTRL_ENET_DIV(12),
> +		       	CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
> +
I'm not sure it's causing the problem you are seeing.  But from i.MX28
spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
be polled for new divider setting?

-- 
Regards,
Shawn