On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Waßmann wrote: > The TX28 derives its PHY clock from the ENET_CLK pin of the > processor. Thus the CLK_ENET_TIME should be enabled by the driver as > mentioned in <20120108033238.GA19721 at S2101-09.ap.freescale.net> > Can you give a web link for that message? -- Regards, Shawn