[PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Will Deacon]

On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
> +static void __init aurora_broadcast_l2_commands(void)
> +{
> +       __u32 u;
> +       /* Enable Broadcasting of cache commands to L2*/
> +       __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
> +       u |= 0x100;             /* Set the FW bit */
> +       __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
> +}

Couple of questions about this code:

1. Is this register r/w from non-secure?
2. I'm surprised that there aren't barriers and/or maintenance operations
   needed around this operation. It might be worth checking in the
   documentation that you have (you probably need at least an isb()
   following the mcr).

Will