[PATCH] ARM: cache-l2x0: add resume entry for l2 in secure mode
21cnbao at gmail.com
Wed Sep 21 01:53:37 EDT 2011
2011/9/21 Shawn Guo <shawn.guo at freescale.com>:
> Hi Barry,
> On Tue, Sep 20, 2011 at 06:57:45PM -0700, Barry Song wrote:
>> we save the l2x0 registers at the first initialization, and restore
>> them after resuming every time.
> I'm unsure that it will work for cases like imx6q, where L2 cache is
> retained and the controller needs to be restored at the very beginning
> of the resume entry (running on physical space).
yes. imx6q actually needs to enable l2 earlier than cpu_resume(and mmu
resume). so how about letting outer_resume support both phy and virt
for example, add early resume: outer_early_resume()
Then for your case, you use asm to "bl out_resume", then "b cpu_resume".
For those chips which lose l2 in suspend cycle, people can call it in
C function after cpu_resume.
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